3981 - Active-HDL: How to resolve unknowns (X) in timing simulation when the RTL simulation is fine and all constraints are met in Place and Route TRACE?

For post-route timing simulation, please set the SDF (Standard Delay Format) value and load as Maximal and Yes, respectively, in Aldec design settings.

i.e.
Step 1: In Aldec Active-HDL, select "Settings" from the Design menu. The Design Settings dialog box will be displayed. Expand the Simulation category and select the SDF subcategory.
Step 2: In the SDF tab, set the SDF value and load as Maximal and Yes, respectively. (see the attached image file)
Step 3: Select Compile All from the Design menu.
Step 4: Select Initialize Simulation from the Simulation menu.

Now, select Simulation >> Run to see the waveforms.

Also, check if the SDF needs a fixed simulation resolution timing setting of say, 1ps.

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3981 - Active-HDL: How to resolve unknowns (X) in timing simulation when the RTL simulation is fine and all constraints are met in Place and Route TRACE?<br>

3981 - Active-HDL: How to resolve unknowns (X) in timing simulation when the RTL simulation is fine and all constraints are met in Place and Route TRACE?<br>

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2715 - Diamond: What does the "potential loop circuits" section of the <em>Place and Route TRACE</em> report mean?

261 - Lattice Diamond: Why is the maximum frequency Fmax in the Place and Route Trace report different from that in the Performance Analyst(PA) report?

1199 - Simulation: ALDEC Active-HDL: What Active-HDL commands can I issue from the command line? <br>

1712 - Diamond: How can user get estimated timing of my design before running place and route?

1200 - Simulation: ALDEC Active-HDL: How can I recompile my testbench without restarting Active-HDL from ispLEVER tool? <br><br>