For running Active-HDL Lattice Edition stand-alone GUI, execute the command "avhdl" from the DOS command window. The following is an example macro file for simulating a Verilog design. The "avhdl" commands are compatible with ModelSim with some minor exceptions. It is generally recommended that "design create" and "design open" be used instead of the "vlib" command in the macro files as shown below:

design create work .
design open work
cd ..\..
set SIM_WORKING_FOLDER .
vlog -v2k -work ./work file1.v file2.v file3.v top.v
vsim work.top -L ovi_ecp3 -PL pmi_work

In the macro file above, file1.v, file2.v, file3.v and top.v are the design files. The top.v is the top-level design. The example assumes that the target is the LatticeECP2 familiy. The "ovi_ecp2" library is the pre-compiled Verilog library for Lattice ECP2. The following are the other pre-compiled FPGA Verilog libraries for other Lattice families:

• ovi_sc
• ovi_ec
• ovi_xp
• ovi_ecp
• ovi_ecp2
• ovi_ecp3
• ovi_machxo
• ovi_xp2

The following is an example macro file for simulating a VHDL design targeted to the Lattice ECP2 family.

design create work .
design open work
cd ..\..
set SIM_WORKING_FOLDER .
vcom -work ./work file1.vhd file2.vhd file3.vhd top.vhd
vsim work.top -L ecp3 -PL pmi_work

The following are the other pre-compiled FPGA VHDL libraries for other Lattice families:

• sc
• ec
• xp
• ecp
• ecp2
• ecp3
• machxo
• xp2