1200 - Simulation: ALDEC Active-HDL: How can I recompile my testbench without restarting Active-HDL from ispLEVER tool? <br><br>

1200 - Simulation: ALDEC Active-HDL: How can I recompile my testbench without restarting Active-HDL from ispLEVER tool? <br><br>

Simulation: ALDEC Active-HDL: For convenience, users may want to make changes to a testbench without exiting Active-HDL. To do this will require the recompiling of the testbench, and restarting the simulation.

The simplest way to recompile the testbench and restart is to issue the commands within the Active-HDL console:

1. Compile the testbench

  • vlog {testbench_name}   //for Verilog
  • vcom {testbench_name} //for VHDL 
2. restart

3. run 100 us (or whatever the simulation time is)

This only recompiles the testbench but does not catch any design changes at lower levels.

The most complete way of doing this from the Active-HDL command line is:

1. Look at the ispLEVER console and find the last command issuance notice. It will look something like:

Launching: 'C:\ispTOOLS7_1\active-hdl\bin\avhdl.exe -do "{testbench_name}_activehdl.do"'

In this case "{testbench_name}_activehdl.do" is the do file that ispLEVER launches ActiveHDL. It will compile everything and launch the simulation. Copy the *.do file name with a Ctrl-C.

2. Go to the AHDL command console and launch the same script via pasting (Ctrl-V) the *.do file name. e.g.

> do {testbench_name}_activehdl.do

This will recompile all and restart the simulation.

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Pertinent to ispLEVER 7.1 or later ispLEVER tools