115 - Active-HDL error: "ELAB2_0093" in mixed Verilog/VHDL design

Description:

This happens when your top-level design is in VHDL but one of the lower-level modules (for example, PLL generated using IP Express) is in Verilog.

Solution:

Take note that Lattice OEM Compiled libraries have different nomenclatures for VHDL and Verilog. For example, "sc" is the SC/M library name for VHDL, and "ovi_sc" is the SC/M library name for Verilog. When you use vsim/asim command, make sure that you use appropriate libraries.

If you are using -L sc, then the PLL will try to match a Verilog parameter to a VHDL generic at the top level. They may be incompatible and you will get the error message. Use -L ovi_sc instead to get rid of the error message.

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115 - Active-HDL error: "ELAB2_0093" in mixed Verilog/VHDL design

115 - Active-HDL error: "ELAB2_0093" in mixed Verilog/VHDL design

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Radiant / Synplify Pro: What output file or log file can the user check to further debug issues related to a mixed language design (i.e. VHDL and Verilog source files) when using Synplify Pro as the synthesis tool?

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Diamond and Radiant version 2023.2 SP1 and older: HDL Parameter set under Active Implementation options not taking effect in VHDL design when using LSE

113 - Active-HDL: How to invoke and use in batch mode?

112 - Active-HDL: How to invoke and use in GUI Mode?