This type of warning is generated during timing simulation, after Place and Route (PAR). The warnings are triggered due to the difference in propagation delay of two or more input signals to a logic gate.
For example, consider a two-input AND gate with input A, B, and output C. The input signals to the AND gate are routed through traces of different lengths in the PLD fabric, causing different propagation delays between these two signals. Even if the drivers of the two input signals are updated at the same time, the logic levels at the input stage of the AND gate will not be updated at the same time due to propagation delay differences.
These glitches are not usually a concern for clock synchronous (RTL) designs. They could be a concern if the output of the gate is directly routed to the SET/RESET or Clock port of a register, causing a false SET/RESET or undesirable clock cycle.