Software Primitives
7738 - Can Global Set/Reset resources be analyzed in Radiant STA tools with Avant?
Global Set/Reset resources cannot be analyzed in STA tools for both Nexus and Avant devices. For the resource's useability, Users may refer to Global Set/Reset Usage for Nexus Platform Application note found in ...
7473 - I2CFIFO Module: Why do I2CFIFO produce glitch when starting an I2C transaction?
Description: When using a slow clock, I2CFIFO module SDA output delay could be too large which may caused SDA glitches to happens during starting of an I2C transaction. Solution: To remove the glitch, user need to set SDA_DEL_SEL:NDelay = 0 with ...
5568 - Diamond/MachXO3: How to use the Lattice primitives in this device family?
DescriptionL Please check the FPGA Libraries Reference Guide. Open Diamond Software -> Start Page -> Look for the "Reference Guides" -> Diamond [DIAMOND VERSION] FPGA Libraries (PDF version) Actual Libraries can be found in the following directories ...
7154 - PMI RAM for Nexus FPGAs: Why is Radiant implementing Large RAM block when using "pmi_ram_dq" and "pmi_family" settings in the design, instead of the EBR block as expected?
If the design requires memory initialization, "pmi_family" parameter should be set to "common". This parameter setting would allow Radiant to build the EBR. For more details, you can refer to Memory Modules User Guide, Chapter 5 (Initializing Memory) ...
6824 - All Nexus: What are the differences between the DCS and the PLLREFCS components?
User can use one or the other. In terms of clock path delay, using the PLLREFCS primitive would give a much shorter delay due to its proximity to the PLL as its primary function is to be used for the PLL. DCS, on the other hand, is located at the ...
7105 - All Nexus: Where can find the description of DELAYA primitive ports name RANKENABLE, RANKSELECT, RANK0UPDATE, RANK1UPDATE which are not found in the documentation?
You can explore the DELAYA page on the Radiant's Help. It shows the parameters name and ports description of the DELAYA primitive. Open Radiant Software--> Help--> Lattice Radiant Software Help--> enter search DELAYA
6274 - CrossLink-NX: How to use the GDDR_SYNC Soft IP?
Please refer to Section 9. Soft IP Modules of the FPGA-TN-02097 (CrossLink-NX High-Speed I/O Interface Technical Note). The said Soft IPs are used in Generic DDR IP depending on the Interface as seen in Table 9.2.Soft IP Used in Each Interface. After ...
6243 - Nexus Devices : How to instantiate a differential input buffer for Nexus devices using Verilog?
Solution: 1.) Below is the syntax using LFCPNX (CertusPro-NX) primitive named IB (Input buffer)
4068 - Diamond / ECP5: What happens to Byte Order when Endian is switched on memories with different port widths?
Solution: In case where the write data width is 36 bits and read width is 18 bits. 1. If Big Endian is selected, first bit 35 to bit 18 are read out, then bit 17 to bit 0 are read out. 2. If Little Endian is selected, first bit 17 to bit 0 are read ...
5897 - CrossLink: Is it possible that the MIPIDPHYA IP core be modified such that these 4 parameters namely CO, CM, CN, TX_FREG_TGT become 4 input ports that can be controlled at runtime?
It is not yet possible. It is a design limitation of the IP to make the 4 parameters to become 4 input ports to be controlled at runtime.
6449 - ECP5/ECP5-5G: What is the effect of DELAYF and DELAYG if inserted into a design?
The DELAYF and DELAYG helps to compensate the clock injection delay from the input pin of the device going to the destination element such as register or flip-flop.