6824 - All Nexus: What are the differences between the DCS and the PLLREFCS components?
User can use one or the other. In terms of clock path delay, using the PLLREFCS primitive would give a much shorter delay due to its proximity to the PLL as its primary function is to be used for the PLL.
DCS, on the other hand, is located at the center of the device as it needs to be close to the DCS_CMUX and within the same distance through each of the clock regions.
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6131 - Certus-Nx: Are the outputs of the Nexus platform's sysCLOCK PLL synchronous signals?
Solution: Yes, the outputs of the PLL (e.g. CLKOP, CLKOS, CLKOS2, etc.) are synchronous signals. But you can introduce dissimilar phase shifts to the outputs, either through static or dynamic mode phase adjustment which is available on the Nexus ...
6429 - All Nexus / ADC: What does the 1.2V internal reference generator is used for ADC reference voltage?
Description: This article explains the purpose of internal reference generator in ADC for all Nexus products. Solution: The 1.2V internal reference generator is provided to facilitate wafer level and package functional testing. With an accuracy of ...
6650 - Nexus : Can we monitor the voltage of Block Ram with Nexus ADC?
Description: The voltage of Block Ram is shared with the Vcc power rail. Also, Block Ram has no sub-power rail to access and monitor it.
6243 - Nexus Devices : How to instantiate a differential input buffer for Nexus devices using Verilog?
Solution: 1.) Below is the syntax using LFCPNX (CertusPro-NX) primitive named IB (Input buffer)
Nexus ADC: At which clock edge are SOC, COG, EOC, and data output captured?
The SOC, EOC, COG signals are acquired on falling edges. The output data should be sampled on the adc_clk rising edge once EOC is high.