6840 - ADC for Nexus FPGAs: Why does ADC DTR (Digital Temperature Readout) data is always 0?
Stretched the pulse width of SOC and COG based on the required ADC clock cycles of conversion to fix the temperature sensing issue.
A. The SOC signal should follow the requirement stated on FPGA-TN-02129 (Section 3.6. ADC Conversion).
"The analog input signal tracking time is controlled by the width of the adc_soc_i pulse, which can have from minimum four ADC sample clock cycles to unlimited number of sample clock cycles."
Note that the ADC clock cycles includes the divider.
Not good Example: Below the minimum 4 ADC clock cycles.