6840 - ADC for Nexus FPGAs: Why does ADC DTR (Digital Temperature Readout) data is always 0?

Stretched the pulse width of SOC and COG based on the required ADC clock cycles of conversion to fix the temperature sensing issue.
A. The SOC signal should follow the requirement stated on FPGA-TN-02129 (Section 3.6. ADC Conversion).
"The analog input signal tracking time is controlled by the width of the adc_soc_i pulse, which can have from minimum four ADC sample clock cycles to unlimited number of sample clock cycles."
Note that the ADC clock cycles includes the divider.

Not good Example: Below the minimum 4 ADC clock cycles.

Good example: within the minimum 4 ADC clock cycles.

B. The user has to wait a certain ADC clock cycles during conversion prior reading the results. Follow the requirement stated on FPGA-TN-02129 (Section 3.6. ADC Conversion).

"One ADC conversion takes at least 25 ADC sample clock cycles corresponding to four sample clock cycles tracking time and the ADC output data becomes available on the falling edge of the sample clock as indicated by the adc_eoc_o (End of Conversion) signal going high."

To get the exact requirement for the wait time prior reading the ADC data, the pulse width of SOC should be substracted to it so the user has to wait at least 21 ADC clock cycles after SOC to ensure to capture valid data.

In this example, COG was stretched to achieve the required conversion time after SOC:

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