6093 - [Nexus Device] ADC: What is the minimum and maximum values for the VCC_ADC?

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• Nexus ADC: At which clock edge are SOC, COG, EOC, and data output captured?

  The SOC, EOC, COG signals are acquired on falling edges. The output data should be sampled on the adc_clk rising edge once EOC is high.

• 6840 - ADC for Nexus FPGAs: Why does ADC DTR (Digital Temperature Readout) data is always 0?

  Stretched the pulse width of SOC and COG based on the required ADC clock cycles of conversion to fix the temperature sensing issue. A. The SOC signal should follow the requirement stated on FPGA-TN-02129 (Section 3.6. ADC Conversion). "The analog ...

• 6429 - All Nexus / ADC: What does the 1.2V internal reference generator is used for ADC reference voltage?

  Description: This article explains the purpose of internal reference generator in ADC for all Nexus products. Solution: The 1.2V internal reference generator is provided to facilitate wafer level and package functional testing. With an accuracy of ...

• 6650 - Nexus : Can we monitor the voltage of Block Ram with Nexus ADC?

  Description: The voltage of Block Ram is shared with the Vcc power rail. Also, Block Ram has no sub-power rail to access and monitor it.

• 6482 - CrossLink-NX: Does LIFCL-40/LIFCL-17 CSFBGA121 has external VREF pin for ADC?

  Solution: Based on Appendix B of FPGA-TN-02129 (ADC User Guide for Nexus Platform), package CSFBGA121 does not support external VREF for both LIFCL-40 and LIFCL-17.