6243 - Nexus Devices : How to instantiate a differential input buffer for Nexus devices using Verilog?

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• 1154 - Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?

  The PLLs in most Lattice FPGAs should operate correctly using a 25 MHz input clock with duty cycles of 33%(low) or 66%(high). Check the data sheet for the specific FPGA you are using to determine the operating limits of the PLL. Look in the data ...

• 6213 - All Nexus Devices : Why PLL IP is not able to meet the BW_FACTOR requirement for more complex cases than dividing or multiplying by 2? For example, reference clock 45MHZ, the output is 11.25 MHz (/4).

  Solution : The Fractional-N Divider option should be enabled if the output is a non-integer multiple of the input frequency.

• 6102 - All Nexus Devices: What is the recovery time of LRAM from de-asserting dps_i?

  There is no such information available. User need to monitor the lramready_o, when this signal assert high, it indicates LRAM is ready for operation.

• 6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

  Users have a couple of options for their design to use the CrossLink-NX evaluation board: 1. Use an external clock from a different clock pin: Instead of using the onboard oscillator, users can connect one of the other PCLK pins as input to the FPGA ...

• 1958 - [LatticeECP3] How do I find the locations of a preferred PLL and its dedicated clock input pin in a LatticeECP3 device?

  In a LatticeECP3 device each dedicated clock input pin is paired to specific PLL. This pairing occurs in a form of a dedicated connection between the clock input pin to that PLL. If a user want to use a PLL directly from a clock input pin, he or she ...