6102 - All Nexus Devices: What is the recovery time of LRAM from de-asserting dps_i?
There is no such information available. User need to monitor the lramready_o, when this signal assert high, it indicates LRAM is ready for operation.
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6243 - Nexus Devices : How to instantiate a differential input buffer for Nexus devices using Verilog?
Solution: 1.) Below is the syntax using LFCPNX (CertusPro-NX) primitive named IB (Input buffer)
6703 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)
6668 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)
6131 - Certus-Nx: Are the outputs of the Nexus platform's sysCLOCK PLL synchronous signals?
Solution: Yes, the outputs of the PLL (e.g. CLKOP, CLKOS, CLKOS2, etc.) are synchronous signals. But you can introduce dissimilar phase shifts to the outputs, either through static or dynamic mode phase adjustment which is available on the Nexus ...
6840 - ADC for Nexus FPGAs: Why does ADC DTR (Digital Temperature Readout) data is always 0?
Stretched the pulse width of SOC and COG based on the required ADC clock cycles of conversion to fix the temperature sensing issue. A. The SOC signal should follow the requirement stated on FPGA-TN-02129 (Section 3.6. ADC Conversion). "The analog ...