5897 - CrossLink: Is it possible that the MIPIDPHYA IP core be modified such that these 4 parameters namely CO, CM, CN, TX_FREG_TGT become 4 input ports that can be controlled at runtime?

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• 6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

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