MPPHY/MPCS
Hold Time Violation in Lattice Avant Designs when using the MPPHY Module
Radiant software automatically inserts LMMI arbiter logic to enable access to the MPPHY LMMI interface. This implementation introduces a LUT4-based clock multiplexer in the LMMI clock path to enable Reveal Controller access to the MPPHY LMMI ...
3024 - What are the various ways to produce RAM/ROM in a design? What is the power up state or content of an inferred RAM?
There are two ways to produce RAM and ROM in a design. You can write code for the design so that the synthesis tool infers the memory or you can instantiate predefined IPexpress or PMI (Parametrized Module Instantiation) memory modules. Inferring ...
3778 - For the MachXO2 EFB (Embedded Functional Block) I2C, when is the TRRDY (Transmit Ready) bit of the I2C Status Register (I2C_1_SR register) set to low for I2C master/slave transaction?
The TRRDY goes low in the following cases: 1. When I2C master is transmitting, the TRRDY goes low whenever you load the Transmit Register (TXDR) with some data, and at the first posedge of the SCL for the next frame, it will go high again. 2. When ...
3013 - What should I do when the LatticeECP3 Delay-locked loop (DLL) is not getting locked?
If the LatticeECP3 Delay-locked loop (DLL) is not locked with the DLL's LOCK signal de-asserted, it means that the DLL's CLKI and CLKFB are not in phase. For example, the DLL input clock may not be stable at that time. It is recommended that the DLL ...
1157 - How many PLLs can use the PLLCAP on the LatticeECP2M FPGA?
The following excerpt is from the LatticeECP2/M sysClock PLL/DLL Design and Usage Guide, TN 1103. --------------------------------------------------------------------- When an external capacitor pin is used by a PLL on one side of the device, it ...
1156 - How can I specify what type of PLL is used for a LatticeECP2/M FPGA?
Beginning in version 7.1 of ispLEVER, the user can specify explicitly whether the software will create a GPLL or an SPLL for the LatticeECP2/M when creating the PLL using IPExpress. This is done with a radio style selector button under the Delay ...
1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?
My design uses 2 PLLs that are cascaded; i.e the output of the 1st PLL is the input of the 2nd PLL. The 1st PLL functions fine in simulations but the 2nd PLL will not achieve lock and the output frequency is not correct. The input frequency of the ...
1154 - Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?
The PLLs in most Lattice FPGAs should operate correctly using a 25 MHz input clock with duty cycles of 33%(low) or 66%(high). Check the data sheet for the specific FPGA you are using to determine the operating limits of the PLL. Look in the data ...
387 - What should I do with the LatticeECP3 DDR3 memory interface VTT termination?
Only external VTT termination should be used for LatticeECP3 DDR3. Use of LatticeECP3's internal on-die termination (ODT) is not recommended. According to the eye diagrams and simulation results from the Lattice factory tests, the recommended ...
386 - What should I do with the unused VTT pads in LatticeECP3 when external VTT termination is implemented?
The answer depends on whether any LVDS input pair is used or not in the bank. 1. If a DDR1/2/3 memory interface is implemented in a LatticeECP3 bank and also includes at least one LVDS input pair, the common mode termination is enabled. In this case, ...
873 - What types of issues could cause the PLL to lose lock?
Situation: A CLKI input frequency to a PLL in a Lattice device is within the normal range for proper PLL operation, yet the PLL loses lock every now and then. Answer: As an example when using a LatticeXP2 device, check that the CLK signal that ...
1412 - Can I implement Error Check Codes in the Embedded Block Ram (EBR) based memory modules?
IPexpress allows you to implement Error Check Codes (ECC) in the Embedded Block Ram (EBR) based memory modules. There is a checkbox to enable ECC in the configuration tab for the module. If you choose to use ECC, you will have a 2-bit error signal ...
1411 - How do I connect the signal "clk_s" in the GDDRX2(X4)_RX(TX).ECLK module for MACHXO2 device?
The "clk_s" signal is a slow clock used for generating the reset synchronization logic of any x2 or higher gearing interfaces. The only requirement of this clock is that its frequency must be slower than the Edge clock(ECLK). Therefore, you can even ...
3815 - For the MachXO2 device, how to make dynamic changes to the PLL output frequency? Can the PLL be dynamically controlled by changing the registers? Is a reset required for the PLL after changing these registers
The MachXO2 device has an option to make dynamic update to the PLL. Registers 0 through 11 are user accessible registers. The remaining registers are reserved for Lattice use or read-only access, and the user cannot write these. For more information, ...
1341 - Does the Analog-Digital Converter (ADC) feature on a Power Manager have an internal averaging or filtering circuit?
The Analog-to-Digital Converter (ADC) on the ispPAC-POWR devices has no internal averaging circuit or filtering circuitry. When used in an electrically quiet system, the ADC will typically have less than one LSB of uncertainty, which corresponds to ...
1332 - Can LatticeECP3 FPGA PLLs accept Spread Spectrum Input clock?
PLLs are designed to track input clocks that have a low frequency drift. The LatticeECP3 FPGA PLLs can accept a spread spectrum clock modulated with low frequency (33KHz). The PLLs while capable of receiving spread spectrum clocks, do not generate ...