1411 - How do I connect the signal "clk_s" in the GDDRX2(X4)_RX(TX).ECLK module for MACHXO2 device?
The "clk_s" signal is a slow clock used for generating the reset synchronization logic of any x2 or higher gearing interfaces. The only requirement of this clock is that its frequency must be slower than the Edge clock(ECLK). Therefore, you can even use the on-chip oscillator to generate this “clk_s” clock.
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