Hold Time Violation in Lattice Avant Designs when using the MPPHY Module

Radiant software automatically inserts LMMI arbiter logic to enable access to the MPPHY LMMI interface. This implementation introduces a LUT4-based clock multiplexer in the LMMI clock path to enable Reveal Controller access to the MPPHY LMMI interface. The additional LUT4 logic can introduce significant clock skew, which may result in hold time violations in user designs. 

In timing report, an unusually large clock skew shall be observed on the affected paths.

 

Upon closer inspection of the clock paths, an extra LUT4 element can be found inserted in the clock network. This LUT4-based clock multiplexer may appear in either the source or destination clock path, contributing to the hold time violations.

Affected IP:

This issue applies to the following Lattice IPs that incorporate the MPPHY module:

1. DisplayPort IP
2. JESD204B IP
3. PCIe x8 IP
4. Ethernets IPs (Tri-Speed, 2.5G, 5G, 10G and 25G)

Affected Radiant version: 25.2 onward

Affected Device: Lattice Avant (LAV-AT)

Bug number: DNG-29323

Solution:

This is a known issue. As a workaround, please try with different Radiant tool settings such as Impose Hold Timing Correction or seeds. If this doesn't help, please contact Lattice support for further assistance. 

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