Issue: Customer only reads ALL-0 input when simultaneously reading and writing on the same address.

Root Cause: Wrong EBR primitive is inferred during synthesis. Instead of PDPSC32K, FIFO32K should be used.

Details/Notes:

• The customer intended to implement a FIFO with First-Word Fall-Through (FWFT) behavior. However, their implemented FIFO design file (genericFifo.vhd) resulted to synthesis tool's inference of the PDPSC32K primitive, instead of the FIFO primitive.

• In a normal non-FIFO operation (how PDPSC32K primitive operates), read port is always prioritized over write port. Therefore, when read and write operation simultaneously occur on the same address, the data read and outputted from the memory will still be the previously stored data (data before write operation). This behavior aligns with the resulting waveforms from the customer's environment. This is on the assumption that EBR mem core is initialized with ALL-0 data, before proceeding with the simultaneous read/write operations. Thus, output read data is always observed to be ALL-0.

• On the other hand, when in FIFO operation, EBR has two operational modes: Normal and FWFT mode.
  • empty_flag = ((write address - read address) == 0)
• When in normal FIFO mode, read operation on an empty FIFO is considered an illegal operation. Therefore, in the customer's environment case, reading and writing at the same time is invalid since, empty flag is asserted (FIFO is empty)
• When in FIFO FWFT mode, when FIFO is empty, then read and write operation occur at the same time, the write data is directly outputted to the read data output port and FIFO remains empty. This is the behavior that is expected out of the customer's environment.

• It should be noted that FIFO FWFT mode is only available in the FIFO32K primitive, and not in any other EBR SW primitives. Also, this feature is only available through Soft IP wrapper, and not in silicon.

Conclusion: The SW tool will never infer the FIFO primitive regardless of the memory design implementation.

Solution:

To resolve the issue, it is advised to

1. With the PDPSC32K primitive inferred and with CER tied to VCC, it is recommended to enable the read/write check insertion. Because when enabled, the synthesis tool inserts bypass logic around the inferred EBR to avoid mismatches caused by indeterminate output values when reads and writes are made to the same address. It can be enabled in two ways
   • Via GUI. In the File List->Strategies->Strategy1->Synplify Pro, check the “Automatic Read/Write Check Insertion for RAM".
   • Using syn_ramstyle attributes.
2. Use Lattice foundation IP, specifically FIFO32K primitive directly in the design, instead of inferencing.