6691 - FIFO_DC IP (Radiant 2023.2 and earlier): How to resolve hold timing violation using the recommended FIFO_DC post-synthesis constraint?

Description:

The result for the hold analysis report is not what we expected for the provided pdc constraint under eval.

This is due to the use of -start.

Solution:

Replacing this -start with -setup or by just removing it will fix the issue.

set_max_delay -from [get_pins -hierarchical */*wp_sync1_r*.ff_inst/Q] -to [get_pins -hierarchical */*wp_sync2_r*.ff_inst/DF] 2

set_max_delay -from [get_pins -hierarchical */*rp_sync1_r*.ff_inst/Q] -to [get_pins -hierarchical */*rp_sync2_r*.ff_inst/DF] 2

set_multicycle_path -from [get_pins -hierarchical */*rd_grey_sync_r*.ff_inst/Q] 2

set_multicycle_path -from [get_pins -hierarchical */*wr_grey_sync_r*.ff_inst/Q] 2

set_multicycle_path -from [get_pins -hierarchical */*rd_addr_r*.ff_inst/Q] -to [get_pins -hierarchical */*rp_sync1_r*.ff_inst/DF] 2

set_multicycle_path -from [get_pins -hierarchical */*wr_addr_r*.ff_inst/Q] -to [get_pins -hierarchical */*wp_sync1_r*.ff_inst/DF] 2

set_multicycle_path -hold -end -from [get_pins -hierarchical */*rd_grey_sync_r*.ff_inst/Q] 1

set_multicycle_path -hold -end -from [get_pins -hierarchical */*wr_grey_sync_r*.ff_inst/Q] 1

set_multicycle_path -hold -end -from [get_pins -hierarchical */*rd_addr_r*.ff_inst/Q] -to [get_pins -hierarchical */*rp_sync1_r*.ff_inst/DF] 1

set_multicycle_path -hold -end -from [get_pins -hierarchical */*wr_addr_r*.ff_inst/Q] -to [get_pins -hierarchical */*wp_sync1_r*.ff_inst/DF] 1

The updated constraint is expected to be updated on Radiant 2022.1 SP1 and Radiant 2023.1

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6691 - FIFO_DC IP (Radiant 2023.2 and earlier): How to resolve hold timing violation using the recommended FIFO_DC post-synthesis constraint?

6691 - FIFO_DC IP (Radiant 2023.2 and earlier): How to resolve hold timing violation using the recommended FIFO_DC post-synthesis constraint?

Related Articles

2631 - ECP3/FIFO_DC: What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?

235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO&nbsp;(FIFO_DC)?

7146 - FIFO_DC IP: Does the LSCC_FIFO_DC have First Word Fall Through(FWFT) feature?

6418 - FIFO for Nexus FPGAs: How does the three FIFO_DC Controller Implementation differs from each other?

5898 - iCE40 UltraPlus: With an iCE40 Ultraplus device, how to drive an external pin with a PLL output using Radiant Software?

235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?