7146 - FIFO_DC IP: Does the LSCC_FIFO_DC have First Word Fall Through(FWFT) feature?

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• 2631 - ECP3/FIFO_DC: What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?

  FIFO_DC is a flexible IP which allows user to translate bus size from write side to read side. Some examples are given to explain how to select Bus Ordering Style. In the case when write data width is 36 bits and read width is 18 bits. 1. Big Endian ...

• 2095 - LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?

  The Big/Little Endian mode switch will affect the word order when read data bus width and write data bus width are set as different values: Case 1: write data bus width is 36bits and read data bus width is 18bits For the Big Endian mode: if write ...

• 6418 - FIFO for Nexus FPGAs: How does the three FIFO_DC Controller Implementation differs from each other?

  1. Controller Implementation = Area-Optimized (HW): Uses a Hardened FIFO controller + Hardened Memory Block for data storage. 2. Controller Implementation =Feature-Rich (LUT) ; Implementation type = EBR: Uses a Fabric-implemented FIFO controller + ...

• 235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?

  Description: The IPexpress tool within Lattice development software allows user to generate FIFO_DC using Embedded Block Ram (EBR) or distributed memory. During the generation of the FIFO_DC module, there are options to use output registers, and/or ...

• 7770 - Avant-AT-G: The instantiated PDPSC32K thru inferring RAM reads ALL-0 input when simultaneously reading and writing on the same address.

  Issue: Customer only reads ALL-0 input when simultaneously reading and writing on the same address. Root Cause: Wrong EBR primitive is inferred during synthesis. Instead of PDPSC32K, FIFO32K should be used. Details/Notes: The customer intended to ...