FIFO_DC is a flexible IP which allows user to translate bus size from write side to read side. Some examples are given to explain how to select Bus Ordering Style. In the case when write data width is 36 bits and read width is 18 bits. 1. Big Endian ...
The Big/Little Endian mode switch will affect the word order when read data bus width and write data bus width are set as different values: Case 1: write data bus width is 36bits and read data bus width is 18bits For the Big Endian mode: if write ...
Description: The IPexpress tool within Lattice development software allows user to generate FIFO_DC using Embedded Block Ram (EBR) or distributed memory. During the generation of the FIFO_DC module, there are options to use output registers, and/or ...
Issue: Customer only reads ALL-0 input when simultaneously reading and writing on the same address. Root Cause: Wrong EBR primitive is inferred during synthesis. Instead of PDPSC32K, FIFO32K should be used. Details/Notes: The customer intended to ...