2631 - ECP3/FIFO_DC: What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?

FIFO_DC is a flexible IP which allows user to translate bus size from write side to read side. Some examples are given to explain how to select Bus Ordering Style.

In the case when write data width is 36 bits and read width is 18 bits.

1. Big Endian selected, bit 17 to bit 0 are first read out, then bit 35 to bit 18 are read out.

2. Little Endian selected, bit 35 to bit 18 are first read out. then bit 17 to bit 0 are read out.

In the case when write data width is 18 bits and read width is 36 bits.

1. Big Endian selected, first word written into FIFO is shown at bit 17 to bit 0 when read out.

2. Little Endian selected, first word written into FIFO is shown at bit 35 to bit 18 when read out.

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2631 - ECP3/FIFO_DC: What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?

2631 - ECP3/FIFO_DC: What's the usage of Bus Ordering Style when using FIFO_DC of Lattice IPExpress which has different data width between write and read port?

Related Articles

235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO&nbsp;(FIFO_DC)?

2095 - LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?

3767 - What is the limit of writing or reading of Single Port RAM for MachXO2 devices? Why&nbsp;can't I&nbsp;find&nbsp;the exact&nbsp;limit on how&nbsp;fast&nbsp;write or read from&nbsp;Single Port RAM can be done?

6901 - iCE40: Can the EBR write clock be asynchronous to the read clock?

6418 - FIFO for Nexus FPGAs: How does the three FIFO_DC Controller Implementation differs from each other?

235 - All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?

3767 - What is the limit of writing or reading of Single Port RAM for MachXO2 devices? Why can't I find the exact limit on how fast write or read from Single Port RAM can be done?