2386 - [Lattice ECP3]: Can I run a DDR3 interface at frequencies as low as 100MHz using LatticeECP3?

Running a DDR3 memory interface at such a low frequency is not supported. It is not only because of the limitation of LatticeECP3 but also due to the DDR3 memory device specification. DDR3 minimum clock cycle requirement is 300MHz or 3.3ns tCK. This is mainly because of the DDR3's internal DLL operation range. When DLL is disabled, tCK(max) can be increased up to 8ns (or down to 125MHz). Without DLL, however, a dedicated memory controller may be required to deal with fluctuating timing.

LatticeECP3 devices also have a DLL specification range of 133MHz to 500MHz. The LatticeECP3 DLL is used to provide a precise 90-degree phase shift for DDR3 write and read operations. If this DLL is running too fast (>500MHz) or too slow (<133MHz), the DLL lock may be released and there may be unknown phase relations.

As a result, a DDR3 interface implemented in LatticeECP3 will not work at these low frequencies. The Lattice DDR3 memory controller IP is designed to operate with the memory DLL enabled, and its operating range is from 300MHz to 400MHz in LatticeECP3 devices.