1156 - How can I specify what type of PLL is used for a LatticeECP2/M FPGA? <BR>

• Related Articles

• 1157 - How many PLLs can use the PLLCAP on the LatticeECP2M FPGA? <BR>

  The following excerpt is from the LatticeECP2/M sysClock PLL/DLL Design and Usage Guide, TN 1103. --------------------------------------------------------------------- When an external capacitor pin is used by a PLL on one side of the device, it ...

• 1154 - <p>Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?<br></p>

  The PLLs in most Lattice FPGAs should operate correctly using a 25 MHz input clock with duty cycles of 33%(low) or 66%(high). Check the data sheet for the specific FPGA you are using to determine the operating limits of the PLL. Look in the data ...

• 1686 - What&nbsp;is&nbsp;the impact and potential problems&nbsp;when&nbsp;the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet? &nbsp;

  It is common for most of today’s FPGA’s to provide multiple PLLs to support the flexible clock requirements needed for today's complex system design. The PLL has a specific frequency operational range. For example, the LatticeXP2 datasheet indicates ...

• 793 - PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?

  Definition: The Lattice FPGA LatticeECP2, LatticeECP2M, LatticeECP3, LatticeSC all have PLL modules. The PLL module has a Lock signal indiating the status of the PLL. For some applications users may use this LOCK signal as a flag or control signal ...

• 5733 - iCE40 Ultra/UltraLite: Can the 48 MHz HFOSC be used as a reference for the internal PLL using iCEcube2 Software?

  Yes, the internal oscillator can be used as a clock source for the PLL. There are specific primitives for this (SB_PLL40_CORE and SB_PLL40_CORE), which will automatically be instantiated when we use the included PLL module generator from iCEcube2 ...