1157 - How many PLLs can use the PLLCAP on the LatticeECP2M FPGA? <BR>
The following excerpt is from the LatticeECP2/M sysClock PLL/DLL Design and Usage Guide, TN 1103.
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When an external capacitor pin is used by a PLL on one side of the
device, it cannot be used by any other PLLs on the same side of the
device. This means that a maximum of two PLLs per device, one on the
left side and one on the right side, can have external capacitors
attached.
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The LatticeECP2M FPGA has one GPLL and 3 SPLLs on the left side of the device and also on the right side. The customer can use all 3 SPLLs on one side of the ECP2M FPGA provided that they all are within the operating specifications for the SPLL. They can also use the GPLL on the same side of the device provided it is within the operation specifications of the GPLL. The operating specifications and capabilities of the SPLL and GPLL are similar but there are some differences to be aware of.
If some of the user's input specifications fall into the area that will require the use of the PLLCAP then the options are more restricted. Only one SPLL or the GPLL on the left side of the device may use the PLLCAP pin.
If the left side GPLL uses the PLLCAP then the 3 SPLLs on that side may not use the PLLCAP. The 3 SPLLs can still be used but the operation must fall within the specification limits for use without the PLLCAP.
Similarly, if the user has an SPLL on the left side that uses the PLLCAP, then the remaining SPLLs and the GPLL on that side may not use the PLLCAP. These other SPLLS and the GPLL can still be used but the operation must fall within the specification limits for use without the PLLCAP.
The following shows an example for valid use of the SPLLs and the GPLL on the left side of the FPGA.
GPLL input = 25 MHz Output = 100 MHz
SPLL1 input = 50 MHz Output = 200 MHz
SPLL2 input = 50 MHz Output = 250 MHz
SPLL3 input = 25 MHz Output = 50 MHz PLLCAP REQUIRED.
Please note that only SPLL3 uses the PLLCAP in this example.
Please also note that the PLL placed on the GPLL in this example can only be used on the GPLL due to the performance operating specifications of the SPLL. The SPLL cannot accept a 25 MHz input without using the PLLCAP and when the PLLCAP is used, the output frequency is limited to 50 MHz or less.