1332 - Can LatticeECP3 FPGA PLLs accept Spread Spectrum Input clock?

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  Description: This article clarifies on SSC generation using PLL in ECP5. Solution: ECP5 device does not support Spread Spectrum Clock (SSC) generation using generic PLL. This feature is, however, applicable only by using SerDes PLL.

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  The following excerpt is from the LatticeECP2/M sysClock PLL/DLL Design and Usage Guide, TN 1103. --------------------------------------------------------------------- When an external capacitor pin is used by a PLL on one side of the device, it ...

• 1154 - <p>Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?<br></p>

  The PLLs in most Lattice FPGAs should operate correctly using a 25 MHz input clock with duty cycles of 33%(low) or 66%(high). Check the data sheet for the specific FPGA you are using to determine the operating limits of the PLL. Look in the data ...

• 1686 - What&nbsp;is&nbsp;the impact and potential problems&nbsp;when&nbsp;the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet? &nbsp;

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• 6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

  Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...