Power Management
128 - What are VCC(VDD)IB and VCC(VDD)OB supply connections used for on LatticeECP2M/3 and LatticeSC/M devices?
Current-Mode Logic (CML) input and output buffers must be terminated for proper operation. CML uses true double termination. Rather than LVDS which is only terminated at the receiver. This means that any signal reflection back to the source reflects ...
2377 - Platform Manager 2 & L-ASC10: What are the allowed input currents for the Power Manager II VMON and digital inputs? Is there a specific recommendation for protecting those inputs?
The VMON inputs need to be protected according to the voltage limits mentioned in the datasheet (<5.9V). This information is contained in the Recommended Operating Conditions table (Page 5 of the POWR1014/A datasheet) ...
5507 - Power Controller: How to turn off the bandgap so that right after the device enters user mode, it will be with the bandgap disabled?
Please follow the following steps: a. Instantiate the "Power Controller" module available from the IPExpress. b. In the IPExpress GUI, select/tick the options "Enable Standby flags", and "Turn off Bandgap when in Standby". c. Now, to turn off the ...
1862 - Power Manager 2: For the open drain outputs, how much leakage current is expected?
For digital outputs 3-14 of the POWR1014/A device the leakage current during the high state will be very low, typically 30 uA or less. During the low state, digital outputs 3-14 can sink up to 1 mA of current and will stay within the specifications ...
5461 - Why is there a high current in the device even if the device is functionally working if VCCIO is powered before Vcc?
The power supply sequence should be strictly followed to ensure proper device operation. One of the reasons the device requires the sequence of power-up is because the device needs to configure/be configured during power-ups. The VCC powers up first ...
5411 - Why does iCE40 devices heats up and have high current consumption when VCCIO and VCCIO2 are applied before VCC?
If we look at the iCE40 datasheets, we can see that there is a correct Power Supply Sequence for the device to operate properly. VCCIO0 and VCCIO2 should only be applied after Vcc has reached a level of 0.5V or greater. Though the device may ...
2209 - [Platform Manager 2] Does VCCD and VCCA need to be above 3.0V when programming the device since the data sheet shows that VCCPROG should between 3.0V to 3.6V?
The POWR1220AT8 will program when the VCCD and VCCA are at 2.8 Volts. The device was characterized across the entire data sheet operating range of 2.8 Volts to 3.96 Volts and this testing included programming of the device. The voltage range for the ...
6431 - ECP5/ECP5-5G: What is the tolerable amount of overshoot/undershoot for ECP5 I/Os?
ECP5 I/Os operates at VCCIOmax of 3.465V with an additional overshoot/undershoot tolerance of +/-180mV for junction temperature at 100degC and +/- 100mV for junction temperature of 125degC without reliability hazard.
6050 - Platform Manager 2: Why does I2C slave address shows 0x78?
0x78 will be acknowledged because the device would think that it is going to get a 10-bit slave address because of the 10bit address scheme In the 10bit address scheme, you require two bytes to transfer the address. After the start condition, a ...
2182 - [Platform Manager 2] Will POR signal be generated when only VCCINP is present and VCCD/VCCA are unavailable, causing a defined state at the OUTx pins?
For proper operation of asynchronous set/resets of our flip-flops, internal POR generation logic is available. This POR circuitry works by detecting voltage levels of the VCCA, VCCD supply lines. The unavailability of analog and digital supply lines ...
1700 - Power Manager II: How do I use the ispPAC-POWR1220's on-board ADC through the I2C port?
To use the ispPAC-POWR1220's on-chip ADC, you must perform the following steps (via I2C): Issue a start conversion command. This is a write to the ADC mux register (0x09) in which you specify the ADC's input channel and the attenuation factor. ...
5983 - Platform Manager 2: How many external DC-DC can be connected with GPIO output?
Controlling various DC-DC enable pins using a single GPIO will be dependent on the internal pull up within the DC-DC. Any number of DC-DC is may be enabled as long as the maximum GPIO source current does not exceed. The other tricky part will be ...
2819 - Power Manager II: Can I use the TRIM output to drive the input of an OpAmp buffer by writing DAC register values via I2C on the POWR1220AT8?
Yes, you can control the TRIM output directly by writing values to the DAC register using the I2C port. To do this you must set the TRIM output in the I2C control mode for profile 0. This can be done with the POWR1220AT8 or the POWR6AT6 device. The ...
2790 - Power manager II: Can we short the inputs of two VMON comparators ( i.e. VMON1 and VMON2) of the Power Manager Device externally on the board for monitoring a supply rail ?
Yes you can short the two VMON inputs of the Power Manager Device externally to monitor a supply rail. However effective Input Resistance (Rin) of the comparators should be considered thoroughly before connecting it to the supply rail. By shorting ...
2721 - Can Power Manager II Device support Hot Socketing?
Yes, Power Manager II device supports Hot Socketing. All the pins of the Power Manager II are Hot Socket complaint. There is no problem in applying maximum specified I/O voltages to the pins before VCCD or VCCA is applied. However small leakage ...
5948 - Platform Manager 2 & L-ASC10: What is the Power ramp rate for L-ASC10?
Power supply ramp rates for all Vcc and Vccio has a minimum of 0.01 V/ms and Maximum of 100 V/ms, as indicated in page 06 of document: FPGA-DS-02036 The VCCA, VCC, VCCIO0, VCCIO1, and VCCIO3 pins should be connected to the same power supply, as also ...
6739 - CrossLink-NX: There is described that "VCCM is an internal supply that is derived from VCCAUX and should measure around 1.25 V", What can we check with VCCM?
VCCM is an internal supply, and it is embedded in the silicon which does not have a connection to the pin. The available pins are enumerated in Section 5.2 of FPGA-DS-02049 or Crosslink-NX Family. Hence, we cannot monitor or access VCCM.
1666 - Power Manager II: Can I use the RESETb pin on a POWR1014 or POWR1220 to reset other parts of my circuit?
The RESETb pin on an ispPAC-POWR1014 or ispPAC-POWR1220 is bidirectional (open drain with internal pull-up). Its primary function is to be used as an input so that one can reset the device after it has been powered up. The secondary function of this ...
2093 - Power Manager 2: Does it allow to read a 1.0 Volt signal from the ADC with attenuator setting 1 (divide by 3) on a PWR6AT6 device?
The POWR6AT6 should be able to read 1.0 Volts from the ADC using either of the attenuator settings (zero or 1). Please insure that the DONE bit (b0 of ADC_MUX) is set to "1" when you read the data or that you have waited the minimum time (Tconvert) ...
1628 - Power Manager II: When using the trim functions of a POWR6AT6, or POWR1220 what happens if I separately disable the LDO or DC-to-DC converter being controlled?
If you disable an LDO or DC-to-DC converter being trimmed bya POWR6AT6 or POWR1220, their trim circuitry will still attempt to perform the trim operation, except that it will now see '0' V as the feedback voltage. This will result in the TRIM output ...
2624 - Platform Manager 2: What will happen if the HVOUT driver current setting in PAC-Designer is less than the actual requirement of the MOSFET?
The HVOUT signal should be connected to the gate of the MOSFET in order to turn it on. There is typically no minimum gate current requirement for a MOSFET in order to turn it on. The current supplied to the MOSFET gate will determine how fast it ...
2040 - Power Manger II: Can the POWR1220AT8 be used to monitor negative voltages?
Description: Yes, the POWR1220AT8 device can be used to monitor negative voltage with the addition of some simple external circuitry. The inputs of the POWR1220AT8 device may accept signals from 0 to 6 V without the addition of external circuitry. ...
2038 - Power Manager II: How much undershoot on the SDA pin can a POWR1220AT8 device endure without causing damaging?
The data sheet shows the Absolute Maximum Ratings for the POWR1220AT8 device. The I2C pins will have the same limits as the digital outputs OUT[5:20] but will also have a digital input buffer. The table shows Vtri, which is the voltage applied to ...
6173 - MachXO3: In the event full device power-down does not proceed or occur, could VCCIO be restored and user-mode resume without performing a device re-configuration?
Description: This FAQ list down the requirement for VCCIO can be restored without device re-configuration. Solution: In the event the VCC and VCCIO0 have been affected by the power-down, all VCCIO will be in off-mode and thus it requires device ...
6172 - MachXO3: Can one bank VCCIO be removed without damaging the part?
Yes, it is safe to remove the non-configuration VCCIO supply. Details: Bank 0 -> Configuration Bank( Stores the configuration Data ) Other Banks-> Non-Configuration Bank VCCIO0 (Bank 0) -> Configuration Bank Supply Voltage : A. The FPGA-TN-02055-2.5 ...
1495 - Power Manager II: Is there an "Boundary Scan Descriptive Language" (BSDL) file available?
Yes, the Lattice website has a page dedicated to Power Manager Devices , Power Manager II"Boundary Scan Descriptive Language", BSDL files are available under "DOWNLOADS" section of the page.
2005 - LatticeECP3: How do I select between the two Vol Max values 0.4V, or 0.2V documented in the LatticeECP3 device datasheet sysI/O Single-Ended DC Electrical Characteristics?
Vol Max is not a user configurable setting. For any of the LVCMOS pin configurations, under normal operating conditions Vol is specified to be a a maximum of 0.4V regardless of the drive strength that the pin was configured. If the current draw falls ...
1476 - Power Manager II: Can I use an ispPAC-POWR1220 for -48V hot-swap control?
Although most of our applications literature shows the ispPAC-POWR607 in -48V hot-swap applications, it is possible to also use an ispPAC-POWR1220. It is generally not preferable to the ispPAC-POWR607 for the following reasons: It is physically ...
6159 - CrossLink: VCCIO0 is up first and internal power good will wait for VCC and VCCaux. Based on the power sequence for Crosslink based on PCN04A-20, does it have a risk of configuration issues or power-up?
Since they already have VCCIO0 (3.3V) powered up first, that part should not be an issue. VCCIO0 is the most important VCCIO to be powered up first. The main reason for the change is that we found VCCaux needs to be powered up last or Crosslink may ...
3828 - iCE40: Is VPP_FAST on ICE40LP CM81 device supported?
No.VPP_FAST on ICE40LP CM81 device is not supported
6150 - iCE40 UltraPlus: What is the VCCIO bank of CRESETB and CDONE on ICE5LP2K-SG48?
The document TN-02001 shows it is in VCCIO2; however, CDONE depends on where the pinout file located and in this case, it is in bank 1 for iCE5LP2K. with the new update on device, it varies which in the case of iCE5LP2K, it is located in bank 1.
6501 - Does Lattice devices have a power-down sequence?
There are no sequencing requirements for the Power-Down of the device. In the event that any supply is powered down below the POR trip point, then all supplies should be powered down before the device can be powered up.
1433 - Platform Manager/Power Manger II: How do I protect VMON input pins from noise or accidental spikes?
The absolute maximum input voltage for the VMON input pins is 6V. Any inadvertent stresses beyond this limit will damage the device. Thus, protection circuits (like using a 5.1V shunt Zener diode) are recommended to guard the VMON input pins against ...
2507 - Lattice Power Manager II: In the Power Manager device, is the output impedance of HVOUT port (in open drain mode) equal to that of the OUT port?
Description: No, the impedance of HVOUT (in the open drain mode) and OUT port is not equal. The design for both the ports is different since HVOUT is designed for higher voltages (10V/12V) and OUT is designed for lower voltages(5.5V). For example ...
6134 - Power Manager II: What is the EECMOS memory size of the POWR1014/A?
Solution: You can find this information in the generated JEDEC file. The number of EECMOS bits is noted in the *QF field. For the POWR1014/A, the size is 13,743.
1402 - Platform Manager 2 & L-ASC10: Do you have any examples of logging power supply faults?
We have several reference designs for Power Manager devices that show how to detect a power supply fault (over voltage or under voltage) and save the data in a SPI memory. Using a current to voltage circuit the fault could also be an over current. ...
1400 - Platform Manager 2 & L-ASC10: What is Hot Swap? And how does a Power Manager device do it?
Hot Swapping refers to inserting or removing a circuit card from a powered backplane. The circuit card presents an almost dead short to the supplies on the backplane with the discharged capacitors (bulk filtering, bypass, and hold-up). This dead ...
1399 - Power Manager II: How does the POWR1220AT8 control a 12V hot swap MOSFET when the maximum HVOUT voltage is 12V?
First of all, only the dash-two (POWR1220AT8-2) Power Manager devices support HVOUT output voltage of 12V. Secondly, the gate of the hot swap MOSFET does need to be driven to 18V to 20V in order to turn it on. This is accomplished using a few ...
1398 - Power Manager II: Is there an evaluation board for the POWR6AT6?
The POWR6AT6 is not featured on a board of it’s own but, it is installed on a couple of evaluation boards for both support and evaluation. The ProcessorPM board has the POWR6AT6 installed with the VMON inputs and Trim-DAC outputs available on the ...
1397 - Power Manager II: How to implement a digitally controlled power supply?
The POWR1220AT8 can be used to implement a form of Voltage Identification Digital (VID). Typically a processor will output a digital code to the power supply to request more or less power depending on the processor load. When the processor is going ...
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