2182 - [Platform Manager 2] Will POR signal be generated when only VCCINP is present and VCCD/VCCA are unavailable, causing a defined state at the OUTx pins?
For proper operation of asynchronous set/resets of our flip-flops, internal POR generation logic is available. This POR circuitry works by detecting voltage levels of the VCCA, VCCD supply lines. The unavailability of analog and digital supply lines results in reset signal assertion even if IO supply (VCCINP) is present. The output pins continue to remain in active reset state even with valid VCCINP level. Open drain OUTx becomes high-Z and HVOUT becomes low. For more details please look in Page 2-23 of the ispPAC-POWR1014/A device datasheet DS1014.