6431 - ECP5/ECP5-5G: What is the tolerable amount of overshoot/undershoot for ECP5 I/Os?
ECP5 I/Os operates at VCCIOmax of 3.465V with an additional overshoot/undershoot tolerance of +/-180mV for junction temperature at 100degC and +/- 100mV for junction temperature of 125degC without reliability hazard.
Related Articles
4657 - ECP2, ECP3, ECP5, MachXO, MachXO2, MachXO3: What is the permitted maximum undershoot/overshoot voltage of a particular device?
Description: Undershoot and overshoot of -2 V to (Vihmax +2) V is permitted for a duration of less than 20 ns. This applies to the following device families: ECP2, ECP3, ECP5, MachXO, MachXO2, MachXO3. For more information, refer to the Absolute ...
2038 - Power Manager II: How much undershoot on the SDA pin can a POWR1220AT8 device endure without causing damaging?
The data sheet shows the Absolute Maximum Ratings for the POWR1220AT8 device. The I2C pins will have the same limits as the digital outputs OUT[5:20] but will also have a digital input buffer. The table shows Vtri, which is the voltage applied to ...
3999 - <p>ispMACH4000 : For ispMACH4000 devices, is the bus-keeper option a global constraint for all the I/Os? When configuring I/O as bus-keeper, what is the signal status on power up?</p>
For the ispMACH 4000V/B/C/Z devices, the bus-keeper option is a global constraint for all I/Os. For ispMACH4000 ZE devices, it is available on per-pin basis. During power up, the I/Os are at default state. After the device enters user mode, the I/Os ...
1827 - LatticeECP3: Does it allow for a multiple I/Os be connected in parallel to have higher combined output current exceeding that of a single
I/O?
LatticeECP3 FPGA 3.3V or 2.5V LVCMOS output pin can support maximum 20mA source or sink current per I/O. In order to support higher current I/O, a user can connect multiple adjacent I/O pins together to produce combined higher source or sink current. ...
1904 - [ispClock 5400D] Are ispClock products suitable for ITU-T G.8262 applications?
No. Although ispClock products have excellent jitter specifications, the dynamics of their PLLs are very different from those used in data transmission applications (such as those based on ITU-T G.8262). The key difference is in PLL loop bandwidth. ...