Wishbone
7481 - MachXO3/MachXO2: Should PB231101 be followed when using EFB at usermode?
Solution: PB231101 applies for for EFB even at usermode. Issue #1: Race condition between CS and MCLK at the end of SPI transaction: This issue occurs even at user mode since EFB block is also involved with this issue. To avoid issue in SPI ...
2565 - MachXO2/MachXO3: When interfacing with the MachXO2 EFB's SPI IP core, how do I avoid data over-flow and under-flow conditions?
Solution: The MachXO2 EFB contains a hard SPI IP core that can be configured as a SPI Master or Slave. The SPI core communicates with the WISHBONE interface through a set of control, command, status and data registers. The SPITXDR (SPI Transmit Data) ...
5534 - Does the ASC10 have to connect to the hardened (primary) I2C interface of the XO2, or can it connect to a secondary I2C (gpio) on the XO2?
A. The Lattice Diamond Programming tool uses the JTAG-to-I2C (primary) interface to program the L-ASC10s. B. The VID component in Platform Designer uses the primary I2C interface to control the Trim-DAC outputs of the L-ASC10s. If you are not using ...
1735 - MachXO2: How can we instantiate the TraceID for Lattice MachXO2 in my VHDL RTL?
You cannot instantiate TraceID directly in your VHDL RTL in your design. You must first instantiate an EFB block and then use either WISHBONE or I2C or SPI protocol to access TraceID. You must remember that only one byte of TraceID is user writable ...
6021 - MachXO3: The I2C engine was continuously generating a clock pulse when forced into an idle state via I2C_1_CR/I2C_2_CR register. Is this an expected behavior? If so, Is there any workaround to move it to an idle state or reset the I2C engine?
Writing the I2C_1_CR/I2C_2_CR register from the system host could rest the logic on the system clock domain but will not rest anything in the SCL clock domain. Issuing a STOP condition from any I2C master via I2C_1_CMDR / I2C_2_CMDR will reset the ...
1702 - MachXO2: Which pin should be used for the EFB SPI clock in a MachXO2 design using the hardened SPI core?
The MachXO2 has 2 hardened SPI cores tied to the internal FPGA configuration logic. These cores can be accessed through an internal bus interface (wishbone) by instantiating the Embedded Function Block (EFB) element in HDL code. The SPI cores have a ...
6833 - MachXO3: Could the LSC_VERIFY_INCR_RTI (0x6A) and LSC_READ_CRC (0x60) commands be used with the XO3LF?
Yes, user can use the LSC_VERIFY_INCR_RTI (0x6A) but not the LSC_READ_CRC (0x60) command.
7098 - MachXO2/MachXO3: When using SSPI to Wishbone RD (FPGA-RD-0219) for MachXO2 failure is experienced when trying to do "Background Erase, Program, and Verify". How to fix it?
Problem: When using SSPI to Wishbone RD (FPGA-RD-0219) background programming fails. How to solve the issue? Solution: When using the SSPI to Wishbone RD for MachXO2, please make sure that GSR for synthesis and map design are turned off.
7275 - MachXO2/MachXO3: Why is the output of the I2C bus of EFB for MachXO2 and MachXO3 gives Hi-Z output at simulation?
Description: When simulating MachXO2/MachXO3 I2C bus, the output in the simulation is only Hi-Z. Solution: The I2C bus of EFB needs a pull up at the test bench in order for proper switching behavior. See below for example implementation at Verilog: ...
7050 - SPI to WISHBONE Configuration Interface Bridge: Where is the SSPI2WB Bridge Reference Design?
SSPI2WB bridge is a custom IP in the reference design which is not available in IP catalog. User may find the Reference design, documentation and source code in MachXO3D page under documentation section. ...