2565 - MachXO2/MachXO3: When interfacing with the MachXO2 EFB's SPI IP core, how do I avoid data over-flow and under-flow conditions?
Solution:
The MachXO2 EFB contains a hard SPI IP core that can be configured as a SPI Master or Slave. The SPI core communicates with the WISHBONE interface through a set of control, command, status and data registers. The SPITXDR (SPI Transmit Data) register holds the byte to be transmitted via the SPI bus. The SPIRXDR (SPI Receive Data) register holds the received byte from the SPI bus. These registers must be written to and read from correctly to avoid data loss. Status bits like SPISR:TRDY/ RRDY provide the timely information. And they can be used to avoid data over-flow and under-flow conditions.
To avoid Transmit-Underrun and Receive-Overrun during SPI transfers, please supply SPITXDR with data (even dummy data) when SPISR:TRDY is asserted. Likewise please read SPIRXDR when there is data (even if 'don't care' data) when SPISR:RRDY is asserted.
Please refer to TN1205 and TN1246 for the details of the SPI transaction with the MachXO2 EFB's SPI IP core. Example SPI transactions showing the EFB register transactions are illustrated in TN1246 (August 2012) Figures 17-18 and 17-19.