3036 - Lattice EPC2/S: Why is the encrypted bitstream not working for Lattice ECP2/S device?<br>
For the encrypted bitstream to work in LatticeECP2/S device, ensure the following:
- For power-up, VCC must reach its valid minimum value before powering up VCCAUX (LatticeECP2/M “S” version devices only). Refer to LatticeECP2/M Family Data Sheet for the minimum VCC: http://www.latticesemi.com/view_document?document_id=21728
- The sysCONFIG interface allows serial input data, using serial configuration mode (SCM) or SPI Serial Flash, or in parallel, using parallel configuration mode (PCM). The connection between the FPGA and the configuration device consists of a clock, chip select(s), a write signal (in PCM), and data. During configuration all data written to the FPGA is ignored until a special preamble is detected in the bitstream. Everything after the preamble is configuration data. The normal preamble is BDB3 (hex), however encrypted bitstreams contain a different preamble. In SCM mode, any CCLK frequencies from 2.5 MHz to 45 MHz are supported, but it is required to stop the CCLK after loading the BAB3 (hex) encryption preamble for minimum 1 ms. Refer to LatticeECP2/M S-Series Configuration Encryption Usage Guide's flow for each sysCONFIG interface: http://www.latticesemi.com/view_document?document_id=25616
- The allowed frequency of the Encrypted Mode CCLK (MHz) for SPI and SPIm is only the subset of the frequency of Non-Encrypted Mode CCLK. Refer to LatticeECP2/M Family Data Sheet for the CCLK frequency: http://www.latticesemi.com/view_document?document_id=21728
- The timing parameters specified in LatticeECP2/M sysCONFIG Port Timing Specifications are met. Refer to LatticeECP2/M Family Data Sheet for the timing parameter: http://www.latticesemi.com/view_document?document_id=21728