7050 - SPI to WISHBONE Configuration Interface Bridge: Where is the SSPI2WB Bridge Reference Design?

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  Setup to enable SSPI in MachX03-9400 development board. Connect to JP2, MCLK, SI, SO, SS, 5V SPI, GND to USBN programming cable. Connect FTDI, do a JTAG chain scan, make sure JTAG can program. Connect USB programming cable. Set to Slave SPI ...

• 7745 - Avant Rev 03x: Why program Quad SPI Flash Programming failed with JTAG2SPI Bridge

  Description User may experience Radiant Programmer fails to perform SPI flash programming via the JTAG2SPI bridge function on Avant Versa RevA Boards populated with Micron MT25QU512ABB8E12-0SIT (Quad) for Avant 03A silicon. There is no issue ...

• 1422 - Can I configure the configuration SRAM memory with the Slave SPI Mode(SSPI)?

  You can not configure the configuration SRAM memory directly with the Slave SPI Mode(SSPI), nor can you read back SRAM memory with the SSPI. But you can use the SSPI to configure the SRAM memory through a REFRESH instruction. The effect is the same ...

• 1702 - MachXO2: Which pin should be used for the EFB SPI clock in a MachXO2 design using the hardened SPI core?

  The MachXO2 has 2 hardened SPI cores tied to the internal FPGA configuration logic. These cores can be accessed through an internal bus interface (wishbone) by instantiating the Embedded Function Block (EFB) element in HDL code. The SPI cores have a ...

• 7098 - MachXO2/MachXO3: When using SSPI to Wishbone RD (FPGA-RD-0219) for MachXO2 failure is experienced when trying to do "Background Erase, Program, and Verify". How to fix it?

  Problem: When using SSPI to Wishbone RD (FPGA-RD-0219) background programming fails. How to solve the issue? Solution: When using the SSPI to Wishbone RD for MachXO2, please make sure that GSR for synthesis and map design are turned off.