7275 - MachXO2/MachXO3: Why is the output of the I2C bus of EFB for MachXO2 and MachXO3 gives Hi-Z output at simulation?

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• 7041 - Diamond 3.9 and All MachXO: Why here is no simulation model for SEDFA/SEDFB Primitive with its support devices?

  Description: After installing Diamond, I find under "xxxx\cae_library\simulation", there not have a simulation model for XO3L SEDFA/SEDFB Primitive. Look into this, I find XO2 device also not have a simulation model for SEDFA/SEDFB Primitive. ...

• 534 - MachXO: Why can't I scan or program the MachXO device on the MachXO Mini board after I programmed my pattern into the device?

  The MachXO JTAG pins on the MACHXO Mini board share the same traces with some generic IOs of the MachXO device (as shown on page 4 and page 2 of the schematic). If the new design patterns have signals driving out of these pins, they could potentially ...

• 1702 - MachXO2: Which pin should be used for the EFB SPI clock in a MachXO2 design using the hardened SPI core?

  The MachXO2 has 2 hardened SPI cores tied to the internal FPGA configuration logic. These cores can be accessed through an internal bus interface (wishbone) by instantiating the Embedded Function Block (EFB) element in HDL code. The SPI cores have a ...

• 2565 - MachXO2/MachXO3: When interfacing with the MachXO2 EFB's SPI IP core, how do I avoid data over-flow and under-flow conditions?

  Solution: The MachXO2 EFB contains a hard SPI IP core that can be configured as a SPI Master or Slave. The SPI core communicates with the WISHBONE interface through a set of control, command, status and data registers. The SPITXDR (SPI Transmit Data) ...

• 7284 - MACHXO3/MACHXO2: What can cause EFB to malfunction in hardware?

  Description: When EFB malfunctions in hardware it is best to check if the EFB is instantiated properly and not optimized. Solution: To workaround this issue, If it is certain that EFB is not optimized, please make sure that GSR is disabled. When GSR ...