5534 - Does the ASC10 have to connect to the hardened (primary) I2C interface of the XO2, or can it connect to a secondary I2C (gpio) on the XO2?

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• 5501 - MachXO3: Can MACHXO3 devices be re-programmed over I2C in User Mode, in addition to access Embedded Function Block (EFB)'s Primary hardened User I2C, along with Primary Configuration I2C?

  Description: This article explores the possibility of MACHXO3 devices be re-programmed over I2C in "User Mode", in addition to access Embedded Function Block (EFB)'s Primary hardened User I2C, along with Primary Configuration I2C. Solution: Both ...

• 1702 - MachXO2: Which pin should be used for the EFB SPI clock in a MachXO2 design using the hardened SPI core?

  The MachXO2 has 2 hardened SPI cores tied to the internal FPGA configuration logic. These cores can be accessed through an internal bus interface (wishbone) by instantiating the Embedded Function Block (EFB) element in HDL code. The SPI cores have a ...

• 1763 - LatticeXP2: Can I connect the SSPIA primitive such that both the JTAG interface and the user logic in the FPGA fabric can access the SSPI Port?

  No, it is not possible to set PERSISTENCE = ON in order to preserve the JTAG to SPI port in the configuration logic while simultaneously using the SSPIA component to access internal configuration logic from the FPGA fabric (PERSISTENCE = OFF). If ...

• 1762 - MachXO2: How do I disable to SPI configuration interface so that an external device can use the SPI pins to talk to the FPGA fabric?

  If a user wants to connect to an external SPI device post configuration without the EFB or Programming logic, then the option "SLAVE_SPI_PORT = DISABLED" should be set. This will allow the SPI pins to be dual-purpose user pins such that the internal ...

• 2043 - LatticeXP2: Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?

  Description: When using the LatticeXP2 device in dual boot mode, the FPGA continuously drives the CSSPIN high. The CSSPIN is considered a dual-purpose pin. However while the CFG0 pin = 0, controlling the dual-boot function, it will cause CSSPIN to be ...