Dual Boot
6425 - The address of Golden is optional, but the address of Primary cannot be specified. If we want to rewrite only Primary in the online configuration data update, which address should we specify?
For the dual-boot, the Primary is configured and located at 0x000000. The jump table is usually located at the last part of the address, thus the jump instruction should not be affected. Please refer to FPGA-TN-02145 sections 3 and 3.1 for Dual Boot ...
105 - How can I determine if a LatticeXP2 FPGA configured from internal flash or from an external SPI flash?
The LatticeXP2 can be setup to operate in dual boot mode. Dual boot mode permits the LatticeXP2 to attempt to load a "working" configuration bitstream, and if that bitstream fails to properly configure the FPGA for a "golden" or "failsafe" bitstream ...
5550 - For the Dual Boot Option, Can the customer use SPI memory space before 0x10000 address since the golden pattern is being stored on the SPI Flash at 0x10000 starting address?
Yes, as long as the primary pattern is saved at the internal flash of the XO2 device, the customer may use the SPI memory available before 0x10000.
1834 - MachXO2: When using the device in Dual-Boot configuration mode, what address should the 'Golden' bitstream image (.bit file) be stored in the external Slave-SPI device?
The 'Golden' bitstream image must be located starting at SPI address 0x010000. If using Lattice ispVM System 18.0 or later, the starting address for the bitstream is entered in the "Starting Address" box of the 'SPI Serial Flash Device' dialog box. ...
3287 - MachXO2: In Dual Boot Programming mode, does programming the external flash erases the internal flash; and does programming the internal flash leave the external flash intact?
Programming the external flash erases the internal flash. However, programming the internal flash does not affect the external flash. For a detailed procedure on dual boot programming, refer to the Dual Boot Demonstration section in EB61, MachXO2 ...
2212 - ECP3: Is there a way to actively select the configuration bitstream the LatticeECP3 loads from the attached SPI memory?
Solution: The LatticeECP3 SPI master configuration logic can be manipulated to provide active control over one of two configuration bitstreams stored in an external SPI memory. A framework for performing this function for the LatticeECP2M is ...
681 - LatticeECP2: How to setup LatticeECP2 dual boot application to load the golden bitstream instead of primary bitstream?
Description: A dual boot application using the LatticeECP2 device has both a golden bitstream act as the golden image, and a primary bitstream act as user image which is periodically updated in SPI Flash. In a typical dual boot configuration ...
5960 - Platform Manager 2 / XO3D: How to get the ASC-10 Dual Boot Document for XO3D?
Please refer to AN6095 Adding Scalable Power and Thermal Management to ECP5 in the section on Dual Boot (multi-boot is mentioned) and FPGA-TN-02039 for ECP5 sysCON-FIG Usage Guide for additional details on multi-boot.
7070 - MachXO5-NX: How to perform Dual-Boot using MachXO5-NX?
See below for steps on how to perform Dual-Boot in MachXO5-NX Background: The current implementation of Dual-Boot is that the JUMP table is found at Address 0.
1663 - MachXO2: How can I force to boot from the “golden boot” image in the external SPI Flash when using the dual boot feature?
The MachXO2 has a dual boot feature that works in an automatic mode. If the image loaded from the internal flash is found to have an issue (CRC error), or if the internal flash is erased, then the part will automatically try to load the golden image ...
7044 - MachXO2/XO3: How to have successful dual-boot with SPI flash with MachXO2/MachXO3 devices?
To have successful dual-boot for MachXO2/MachXO3 please change CRC settings of the generated bitstream of Lattice Diamond Software using the Deployment tool. See below for the steps: 1.Open Deployment Tool then select File Conversion and Bitstream:
6597 - Crosslink-NX: What is the boot-up time for the Crosslink NX device?
In datasheet, it is mentioned that "Instant-on configuration – IO configures under 3 ms". The boot-up time is based on estimation with respect to the following parts: power ramp time, config Post Power-up Test (self-test and trimming) time, bitstream ...
2043 - LatticeXP2: Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?
Description: When using the LatticeXP2 device in dual boot mode, the FPGA continuously drives the CSSPIN high. The CSSPIN is considered a dual-purpose pin. However while the CFG0 pin = 0, controlling the dual-boot function, it will cause CSSPIN to be ...
334 - How can user determine which image is loaded into FPGA if the primary and golden images are identical for dual boot?
No. The only possible way to implement this is to use an IO pin to identify the image. For example, the user's FPGA designs could include logic to drive this pin to different logic levels for the different images. This pin is part of the user design ...
6527 - iCE40 LP/HX: Does iCE40 LP384 support SB_WARMBOOT device configuration primitive?
SB_WARMBOOT is supported for all iCE40 Devices except for the iCE40-LP384.
3817 - LatticeXP2: Is the download/configuration time from Internal/External SPI Flash different while using Dual Boot Mode in LatticeXP2 device?
While using Dual Boot Mode, the configuration time (time required for the bitstream to get configured inside the device) from Internal Flash is less. Data transfer is faster because the Internal Flash interface with SRAM is parallel, whereas it is a ...
6908 - How is the CRC the bitstream (.bit) file checked in the config logic of the FPGA?
A CRC error is caused by incorrect or corrupt data. Data is read from the primary image in rows. As each row enters the Configuration Engine the data is checked for CRC consistency. Before the data enters the Configuration SRAM the CRC must be ...