6908 - How is the CRC the bitstream (.bit) file checked in the config logic of the FPGA?

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  Yes, XO3LF have a CRC frame on the bit file. It is shifted when using the LSC_BITSTREAM_BURST command. See CRC highlighted in red on the bit file and on the SVF file.

• 5882 - MachXO2, MachXO3, MachXo3D: What is the complete list of Status Bit Register and their description?

  Bit 0: JTAG TRANSPARENT Mode This bit will be set to '1' if the device is currently in Transparent mode. Bit [3:1]: Config Target Selection By default the configuration SRAM array (Bit [3:1] = 000) is selected as the target. Bit 4: JTAG Active This ...

• 6186 - Lattice Radiant Programmer: How user can Flash FPGA binary file (.rbt) and Propel SDK (RISC-V) binary file to Lattice FPGA?

  To flash FPGA binary file (.rbt) user can use the provided C source code in the Lattice software installation directory for embedded programming. C source code for Radiant: <install_path>\programmer\embedded_source Example: C:\lscc\radiant\<Radiant ...

• 452 - LatticeXP2: Why doesn't the USERCODE assigned using Spreadsheet View match the value retrieved from a LatticeXP2 programmed with an encrypted bitstream?

  The program that creates the FPGA bit stream encrypts the USERCODE in addition to the data used to configure the LatticeXP2. After the LatticeXP2 FPGA is programmed the USERCODE can be retrieved from the LaticeXP2. The value is available from either ...

• 105 - How can I determine if a LatticeXP2 FPGA configured from internal flash or from an external SPI flash?

  The LatticeXP2 can be setup to operate in dual boot mode. Dual boot mode permits the LatticeXP2 to attempt to load a "working" configuration bitstream, and if that bitstream fails to properly configure the FPGA for a "golden" or "failsafe" bitstream ...