3287 - MachXO2: In Dual Boot Programming mode, does programming the external flash erases the internal flash; and does programming the internal flash leave the external flash intact?
Programming the external flash erases the internal flash. However, programming the internal flash does not affect the external flash. For a detailed procedure on dual boot programming, refer to the Dual Boot Demonstration section in EB61, MachXO2 PICO Development Kit User's Guide.
Related Articles
3817 - LatticeXP2: Is the download/configuration time from Internal/External SPI Flash different while using Dual Boot Mode in LatticeXP2 device?
While using Dual Boot Mode, the configuration time (time required for the bitstream to get configured inside the device) from Internal Flash is less. Data transfer is faster because the Internal Flash interface with SRAM is parallel, whereas it is a ...
Radiant Programmer: What is Erase, Program, Verify Quad 1 operation used for?
Description: Erase, Program, Verify Quad 1 enables that QE bit to '1'. In general, there are two (2) requirements/steps to enable booting from external SPI Flash through x4 (QUAD Mode) Step 1 - Convert the bitstream file into hex (Quad I/O read mode) ...
1663 - MachXO2: How can I force to boot from the “golden boot” image in the external SPI Flash when using the dual boot feature?
The MachXO2 has a dual boot feature that works in an automatic mode. If the image loaded from the internal flash is found to have an issue (CRC error), or if the internal flash is erased, then the part will automatically try to load the golden image ...
7315 - MACHXO3: Why I cannot perform SPI programming after enable dual boot to configure from external SPI flash
Description: MACHXO3 device share the same SPI SysConfig ports for both SSPI and MSPI configuration mode. The Configuration(CFG) MSPI is designed to be bus friendly, i.e. when it's not actively booting, all MSPI pins are tri-stated. It's possible to ...
2043 - LatticeXP2: Can the CSSPIN pin be used as a GPIO in dual-boot mode on the LatticeXP2 device?
Description: When using the LatticeXP2 device in dual boot mode, the FPGA continuously drives the CSSPIN high. The CSSPIN is considered a dual-purpose pin. However while the CFG0 pin = 0, controlling the dual-boot function, it will cause CSSPIN to be ...