ADC Core Module
Understanding ADC Calibration and Accuracy Using %FS_ADC on the Nexus Platform
Understanding ADC Calibration and Accuracy When working with precision analog-to-digital conversion (ADC) systems, especially in low-voltage applications, achieving accurate and repeatable results is critical. Customers often encounter discrepancies ...
7784 - Nexus ADC: At which clock edge are SOC, COG, EOC, and data output captured?
The SOC, EOC, COG signals are acquired on falling edges. The output data should be sampled on the adc_clk rising edge once EOC is high.
6441 - PLL for Nexus FPGAs: How to dynamically change the PLL output frequency?
Description: On FPGA-TN-02095, locate Appendix C. PLL LMMI Operation. The user can access the PLL dynamic parameters through the use of LMMI (Lattice Memory Mapped Interface). Solution: If the user wants to vary the output frequency (for example ...
6840 - ADC for Nexus FPGAs: Why does ADC DTR (Digital Temperature Readout) data is always 0?
Stretched the pulse width of SOC and COG based on the required ADC clock cycles of conversion to fix the temperature sensing issue. A. The SOC signal should follow the requirement stated on FPGA-TN-02129 (Section 3.6. ADC Conversion). "The analog ...
6650 - Nexus : Can we monitor the voltage of Block Ram with Nexus ADC?
Description: The voltage of Block Ram is shared with the Vcc power rail. Also, Block Ram has no sub-power rail to access and monitor it.
6510 - CrossLink-NX: What is the accuracy of ADC Internal Reference Voltage?
Description: The accuracy of the ADC Internal Reference Voltage (VREFINT_ADC) value is +/-5%.
6482 - CrossLink-NX: Does LIFCL-40/LIFCL-17 CSFBGA121 has external VREF pin for ADC?
Solution: Based on Appendix B of FPGA-TN-02129 (ADC User Guide for Nexus Platform), package CSFBGA121 does not support external VREF for both LIFCL-40 and LIFCL-17.
6093 - [Nexus Device] ADC: What is the minimum and maximum values for the VCC_ADC?
VCC_ADC which is 1.0V follows the same voltage minimum and maximum range of VCC.