6510 - CrossLink-NX: What is the accuracy of ADC Internal Reference Voltage?

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• 6429 - All Nexus / ADC: What does the 1.2V internal reference generator is used for ADC reference voltage?

  Description: This article explains the purpose of internal reference generator in ADC for all Nexus products. Solution: The 1.2V internal reference generator is provided to facilitate wafer level and package functional testing. With an accuracy of ...

• Nexus ADC: At which clock edge are SOC, COG, EOC, and data output captured?

  The SOC, EOC, COG signals are acquired on falling edges. The output data should be sampled on the adc_clk rising edge once EOC is high.

• 6482 - CrossLink-NX: Does LIFCL-40/LIFCL-17 CSFBGA121 has external VREF pin for ADC?

  Solution: Based on Appendix B of FPGA-TN-02129 (ADC User Guide for Nexus Platform), package CSFBGA121 does not support external VREF for both LIFCL-40 and LIFCL-17.

• 6436 - PLL: What is the recommended accuracy to obtain a stable reference clock as the D-PHY hard core PLL input?

  Description:The PLL of the D-PHY hard core will need a stable reference clock as its input. Does Lattice have a recommended accuracy for this reference clock? Solution:There are no specific guidelines as to the recommended accuracy for the reference ...

• 6430 - CertusPro-NX / ADC: Why is a PLL used to drive the ADC adc_clk_i pin and not directly driven by an oscillator output?

  Description:This article explains the reason ADC clock-in cannot be driven using an oscillator output in CertusPro-NX. Solution:In CertusPro-NX., the ADC clock input is hard-wired on the fabric to the 4th secondary output (CLKOS4) of the Lower Right ...