JTAG
5499 - Is there a lower power state that the user can maintain when power is first supplied?
The user could delay the device configuration itself by holding LOW either PROGRAMN or the INITN pin when applying a power. However, this cannot tell how much power it would. consume in this state, because it is dependent on the board conditions, the ...
1323 - Is PROGRAMN pin independent of JTAG programming operations?
The PROGRAMN pin does not affect the JTAG state machine or boundary scan cells. However, the PROGRAMN pin does clear the SRAM configuration memory of the device. Because of this, a logic low signal on PROGRAMN pin at any time during JTAG ...
1263 - Can the PROGRAMN pin be held low for a period of time during power-up to prevent the FPGA from configuring?
Yes, PROGRAMN pin can be used to hold FPGA from configuring. The are cases where user is using SPI programming mode and would like to control the exact time to begin configuration with PROGRAMN pin. Lattice FPGA enter configuration mode when one of ...
1129 - How many additional clocks are required after the bitstream is sent in with slave configuration modes?
For Slave Serial mode, no additional clocks are required as the number of clocks used to serially shift the bitstream into the device is sufficient. For Slave Parallel mode, at least four additional clocks should be sent after the bitstream is ...
1864 - MachXO2: In Self-Download Mode, how does the DONE signal behave?
DONE will assert when the device is successfully configured from the internal CFG flash. For complete information regarding the Programming and Configuration of the MachXO2 device, please refer to the MachXO2 Programming and Configuration Guide.
3336 - MachXO2: what is the difference between "Flash erase, program, verify, secure" and "Flash erase, program, verify, secure plus"?
"FLASH Erase, Program, Verify, Secure" works as the following steps. 1. Erase the flash 2. Program the flash 3. Verify the flash 4. Secure the device by programming the Security bit This operation will secure the CFG Flash Sectors. For example, user ...
3293 - MachXO2: Is it possible to program the UFM block iteratively without erasing it, with the understanding that bits already programmed stay programmed?
The erased UFM contains all 0s. Hence, a '0' to '1' transition is possible with a write command whereas going from a '1' to a '0' requires an erase operation. An Erase command erases the sector. For example: 0xFE -> 1111 1110 to 0xFC -> 1111 1100 ...
6036 - MachXO3: Is it possible that Flash USERCODE and SRAM USERCODE can be different during programming and read mode?
This is theoretically possible but in the Lattice Programming this is set to be identical regardless of SRAM and Flash programming.
7137 - MachXO2/MachXO3: Why are there excess lines of pages in jed file vs the documented CFG programmable pages?
Extra pages found in the actual bitstream is not part of the configuration data but is used for EOF handling. Though it is not part of the configuration data, it should still be programmed.
6394 - How to resolve the JTAG read/write access issue with Lattice's FPGA that uses JTAG voltage other than 3.3 V?
Description: Device Constraint Editor Global Bank VCCIO setting for Bank0 & Bank1 "CONFIGIO_VOLTAGE_BANK0/CONFIGIO_VOLTAGE_BANK0" is set to "Auto" by default and the voltage is 3.3V. Solution: To workaround on this, user need to assign the correct ...
7336 - Lattice Radiant v2023.2: How to modify I2C slave address or 96-feabits using Pseudo mode?
Description: Nexus device family has a default I2C slave address of 0x40 and you are allow to modify it based on your requirement. Solution: To permanently modify the I2C address, you can modify the desired value in .fea file and use the Programmer ...
6297 - All Nexus: How to solve the issue regarding SRAM erase? Error: "Failed to erase the SRAM..."
Description: One of the possible causes is that the flash is configuring the SRAM and thus causing access issue with FPGA's SRAM. Solution: To workaround this issue, user may try the following: (1) Hold the PROGRAMN port to 0 (active state/asserted) ...
7095 - MachXO3/XO5: What is the IO state for configuration pins when MachXO3 device entered offline programming mode?
Offline programming mode involves erasing the content of the SRAM which makes the device returns to hardware default mode where the I/O state return to its default configuration which is tri-stated with weak pull-down to GND (some pins such as ...
2714 - ICE40: What are the programming modes available in LatticeiCE40 device?
The LatticeiCE40 device has the following programming modes : SPI Master: In this mode, a standard SPI Flash is connected to the Device , and the device boots from the external SPI Flash using SPI Master configuration Interface. This is the best ...
6260 - Radiant version 3.0 or earlier: How to solve Nexus Platform SRAM programming issue?
Description: In Radiant 3.0 or earlier version, the sysConfig has default setting for the JTAG_PORT as DISABLED. So it could lead to JTAG access issue on the device after loading the generated bitstream into the SPI Flash. Solution: As a workaround, ...
7266 - MachXO2/MachXO3:How to reset device ID when it was accidentally changed during programming?
Description: When using external programmer, it can sometimes cause an issue that the device ID is accidentally changed due to sending of wrong bits.
6238 - Lattice Programmer Tool: How to program Lattice FPGA using Programmer?
1. Open Lattice Radiant/Diamond Programmer. 2. Detect the programming cable: -Click "Detect Cable" on most right corner, then choose the first port if you are using only 1 FTDI USB cable. The sequence always starts at 0 which is the allocated address ...
2077 - LatticeECP3: Can the default BSDL file provided on the Lattice website be used to test a programmed LatticeECP3 device after reinitialization?
Description:For LatticeECP3, the IO personality latches which is the I/O electrical properties such as Drive strength, buffer enable paths, open-drain, pullup/down/keeper is preserved after initial programming. These SRAM cells are not cleared by any ...
7210 - MACHXO3D: How to enable MACHXO3D SDM Port INITN/DONE/PROGRAMN persistence mode?
Description: MACHXO3D SDM Port INITN/DONE/PROGRAMN are dual purpose pins, which can be use as GPIO in user mode based on persistent mode settings. Solution: These are part of Feature Row settings and Feature Row bits that must be programmed to take ...
6195 - How do I program Lattice FPGA device?
To workaround on this, user may follow the following steps: Go to Run menu > Scan Device Detect Cable Set Programming Speed Settings > Use custom clock Divider > TCK Divider Setting = 5. If user is programming the SRAM, select the following ...
6179 - How do user program Lattice FPGA after programming a bitstream to the SPI Flash with JTAG_PORT and MASTER_SPI_PORT set to DISABLED?
Description: When JTAG_PORT and MASTER_SPI_PORT is set to DISABLED, user can no longer access the configuration logic through JTAG and MSPI Port. Thus, user can't perform programming with the interface. Solution: To workaround on this, user can ...
6162 - How to solve "No Lattice cable detected on any port" and no detect cable on the GUI in newly installed Ubuntu 20.04.3?
The following procedures will serve as guide from the software installation process until the cable driver setup: 1. Install fresh Ubuntu 20.04.3 LTS. 2. Install Lattice Radiant. If you encounter “xcb” error use the following commands: sudo apt-get ...
6909 - MachXO3LF: What commands can we used on our SVF file to verify that we have written correct configuration into the SRAM?
There are 2 ways to check if user have written correctly into the SRAM of the MachXO3LF: 1. LSC_BITSTREAM_BURST (0x7A): Using this command to program, the device will automatically check the CRC. User can then monitor the Status register or the DONE ...