6394 - How to resolve the JTAG read/write access issue with Lattice's FPGA that uses JTAG voltage other than 3.3 V?
Description:
Device Constraint Editor Global Bank VCCIO setting for Bank0 & Bank1 "CONFIGIO_VOLTAGE_BANK0/CONFIGIO_VOLTAGE_BANK0" is set to "Auto" by default and the voltage is 3.3V.
Solution:
To workaround on this, user need to assign the correct voltage in CONFIGIO_VOLTAGE_BANK0/CONFIGIO_VOLTAGE_BANK0 that matches the JTAG voltage in order to enable JTAG read/write access.
Related Articles
6121 - Does the Nexus Platform family have an internal access to the configuration area (ex: USERCODE, Unique ID, CFG0, CFG1, etc)?
Referring to the Table 6.14 in FPGA-TN-02099 for non-JTAG command table, this is the command sets for all non-JTAG configuration ports including LMMI. The command sequence should be no difference as described in FPGA-TN-02099 for NON-JTAG slave ...
7026 - MachXO5-NX: How to fix read access issue with Flash Access IP when lmmi_clk_i is 50 MHz?
Problem: When using internal flash in hardware, reading is wrong when using 50 MHz lmmi_clk_i. Solution:When experiencing an issue with Flash Access IP at 50 MHz clock, update CONFIG_IOSLEW setting at Device Constraint Editor from SLOW to FAST. See ...
6186 - Lattice Radiant Programmer: How user can Flash FPGA binary file (.rbt) and Propel SDK (RISC-V) binary file to Lattice FPGA?
To flash FPGA binary file (.rbt) user can use the provided C source code in the Lattice software installation directory for embedded programming. C source code for Radiant: <install_path>\programmer\embedded_source Example: C:\lscc\radiant\<Radiant ...
1763 - LatticeXP2: Can I connect the SSPIA primitive such that both the JTAG interface and the user logic in the FPGA fabric can access the SSPI Port?<quote><quote></quote></quote>
No, it is not possible to set PERSISTENCE = ON in order to preserve the JTAG to SPI port in the configuration logic while simultaneously using the SSPIA component to access internal configuration logic from the FPGA fabric (PERSISTENCE = OFF). If ...
2125 - What is the device programming time of a Lattice FPGA?
Solution: The time to program a Lattice FPGA is dependent on several factors including configuration mode, programming speed, and device size. Some configuration modes and methods are faster than others. The complete configuration time inherently ...