7026 - MachXO5-NX: How to fix read access issue with Flash Access IP when lmmi_clk_i is 50 MHz?
Problem: When using internal flash in hardware, reading is wrong when using 50 MHz lmmi_clk_i.
Solution:When experiencing an issue with Flash Access IP at 50 MHz clock, update CONFIG_IOSLEW setting at Device Constraint Editor from SLOW to FAST. See below:
Related Articles
7070 - MachXO5-NX: How to perform Dual-Boot using MachXO5-NX?
See below for steps on how to perform Dual-Boot in MachXO5-NX Background: The current implementation of Dual-Boot is that the JUMP table is found at Address 0. We are changing the implementation of Dual-Boot as below. For this new implementation, the ...
6917 - MachXO5-NX: How to speed up the MachXO5-NX (LFMXO5-25) boot/configuration time through its internal flash?
See below steps to significantly improve the boot/configuration time from internal flash: 1.) In your source project, generate a bitstream that contains the following: * Set the FLASH_CLK_FREQ = 112.5MHz * Set CONFIG_IOSLEW = FAST 2.) *Launch the ...
6394 - How to resolve the JTAG read/write access issue with Lattice's FPGA that uses JTAG voltage other than 3.3 V?
Description: Device Constraint Editor Global Bank VCCIO setting for Bank0 & Bank1 "CONFIGIO_VOLTAGE_BANK0/CONFIGIO_VOLTAGE_BANK0" is set to "Auto" by default and the voltage is 3.3V. Solution: To workaround on this, user need to assign the correct ...
6260 - Radiant version 3.0 or earlier: How to solve Nexus Platform SRAM programming issue?
Description: In Radiant 3.0 or earlier version, the sysConfig has default setting for the JTAG_PORT as DISABLED. So it could lead to JTAG access issue on the device after loading the generated bitstream into the SPI Flash. Solution: As a workaround, ...
6121 - Does the Nexus Platform family have an internal access to the configuration area (ex: USERCODE, Unique ID, CFG0, CFG1, etc)?
Referring to the Table 6.14 in FPGA-TN-02099 for non-JTAG command table, this is the command sets for all non-JTAG configuration ports including LMMI. The command sequence should be no difference as described in FPGA-TN-02099 for NON-JTAG slave ...