Generic DDR / SDR
2637 - ECP3: Can on-chip parallel termination to TT be used when implementing Generic DDR interface on LatticeECP3 device?
Description: An on-chip parallel termination to VTT can be used when implementing Generic DDR interface on LatticeECP3 device. However, the same is not possible for DDR interfaces. External termination to VTT is required for DDR interfaces. All DQ ...
2519 - LatticeECP3 : Why does LatticeECP3 Generic DDR (Double Data Rate) design generates missing attribute errors?
IDDRAPPS and ODDRAPPS attributes are required for all DDR interfaces to indicate the type of interface being generated by the software. When the DDR interface is generated through IPexpress it will generate HDL that includes the correct values for ...
2386 - [Lattice ECP3]: Can I run a DDR3 interface at frequencies as low as 100MHz using LatticeECP3?
Running a DDR3 memory interface at such a low frequency is not supported. It is not only because of the limitation of LatticeECP3 but also due to the DDR3 memory device specification. DDR3 minimum clock cycle requirement is 300MHz or 3.3ns tCK. This ...
6815 - CertusPro-NX: Can I use GDDRX1 IO logic on IO bank 0?
Bank 0 does no support GDDRX1 function, Banks located on Left and Right side of the device (for WRIO bank) support such functionality. Hence, it is confirmed that this is a hardware limitation due to hardware delay constraint.
7096 - DDR: Can the "DDR_Generic" Module in Lattice Radiant and Diamond software which has DDR communication supports bidirectional input and output?
The Generic Double Data Rate Input/Output (GDDR I/O) Module has separate receive DDR interface and transmit DDR interface, it doesn't support the use of GDDRx1 pin as input and the same pin as output. The 'Interface Type' option in IP Catalog for DDR ...
5812 - ECP5/ECP5-5G: The clarity designer automatically selects DDRX1 for frequencies = 200MHz and DDRX2 for frequencies >200Mhz. Since the datasheet for DDRX1 allows 200Mhz to 250Hz, how can we select DDRX1 for clock frequencies between 200Mhz and 250
It is possible that the selection between GDDRX1 and GDDRX2 by Clarity considers both the DDR interface performance and the internal fabric performance. For example, for 500Mbps, DDR hardware is OK for both GDDRX1 and GDDRX2. But GDDRX1's SCLK runs ...
2530 - Generic DDR Simulation: glitches in functional simulation, but not in timing simulations for an output DDR (Double Data Rate) interface
Description: In the GDDRX2_TX Aligned interface, the ECLKSYNC, CLKDIV, DQSBUFE1 and SCLK routing delay timing will generate the required phase relationship between SCLK and DQCLK1 inside the ODDRX2D module so data will be correctly transferred ...