G8B10B PCS
[ECP5UM WORKAROUND] The PCS' lsm_status signal is not asserting
Modify the rdo_rx_pcs_rst_c logic based on the RSL documentation. 1. Open the *_softlogic.v, look for the rdo_rx_pcs_rst_c. Add the input for the OR logic such as rdi_rx_los_low_s, rdi_rx_cdr_lol_s and rui_rx_pcs_rst_c. 2. Open the IP RTL ...
697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?
When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data. During the time the RX clocks are unstable, the pointers on the PCS RX FPGA interface FIFO (RX FIFO) can reach ...
1833 - LatticeECP3: In a design that uses generic 8b10B protocol, Is there any example design that uses 16-bit word alignment?
Lattice does not have an example 16-bit word alignment code. It is recommended to use the PCS module in IPexpress within the Lattice Diamond software tools to generate the 16-bit word alignment verilog code. Information about the PCS module and ...
7170 - CertusPro-NX/MPCS: In a multiple lane MPCS-G8b10b design, why does RX lanes shows all zero data?
Solution: In case encountering this kind of issue the potential workaround is to create multiple single-instance of PCS-G8b10b per channel. If in doubt how to implement this, kindly contact techsupport@latticesemi.com.
2099 - LatticeECP3: Is it allowable to bypass the PCS & 8B10B encoding/decoding function and still use the CTC FIFO?
The CTC input needs to be 8b10b decoded data (a K-control bit, and an 8-bit hexadecimal character). If 8b10b decoder is bypass, the data at the input to the CTC block will be 10-bit encoded 8b10b data. So, it cannot use the CTC functionality when the ...
6977 - [CertusPro-NX] Serdes/PCS: Why does the MPCS-8b10b IP fails in x8 lane simulation?
Solution: The issue has been fixed in Radiant 2023.2 (MPCS IP version 1.4.2 or later).
6965 - Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock frequency?
Description: From FPGA-TN-02245-1-1-CertusPro-NX-SerDes-PCS-User-Guide of the Appendix C. Calculating Parameters for SerDes PLL, it shows the available data rates with respect to the reference clock. However in any case that the desired data rate for ...