When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data. During the time the RX clocks are unstable, the pointers on the PCS RX FPGA interface FIFO (RX FIFO) can reach ...
Lattice does not have an example 16-bit word alignment code. It is recommended to use the PCS module in IPexpress within the Lattice Diamond software tools to generate the 16-bit word alignment verilog code. Information about the PCS module and ...
Solution: In case encountering this kind of issue the potential workaround is to create multiple single-instance of PCS-G8b10b per channel. If in doubt how to implement this, kindly contact techsupport@latticesemi.com.
The CTC input needs to be 8b10b decoded data (a K-control bit, and an 8-bit hexadecimal character). If 8b10b decoder is bypass, the data at the input to the CTC block will be 10-bit encoded 8b10b data. So, it cannot use the CTC functionality when the ...
Description: From FPGA-TN-02245-1-1-CertusPro-NX-SerDes-PCS-User-Guide of the Appendix C. Calculating Parameters for SerDes PLL, it shows the available data rates with respect to the reference clock. However in any case that the desired data rate for ...
Lattice Technical Support Expectation Please be advised that highest priority for Lattice Technical Support will be given to 1. Software which is not working as expected or suspected bugs. We recommend that customers use the latest software tools and ...
Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...
Glitch Fliter is used to prevent short-duration events of glitches, This is used to prevent False tripping on noise in a system. GLITCHFilter in device constraints , enables 1ns glitch filtering.
Description: Nexus device family has a default I2C slave address of 0x40 and you are allow to modify it based on your requirement. Solution: To permanently modify the I2C address, you can modify the desired value in .fea file and use the Programmer ...
Description: To understand the RTL formatting of the PCIe configuration space in the Nexus' PCIe demos, please refer to the following details. Figure 1 illustrates the initialization of the PCIe configuration space in the Nexus' demo.