Configuration registers of Tri-Speed Ethernet MAC (TSMAC) IP Core can be accessed through Host Interface. Also, values for particular registers can be hard coded in the ts_mac_core.v file if you are not using any host interface module in your design.
The SGMII and Gb Ethernet PCS IP "xmit_autoneg" signal does not have the same definition as the xmit variable defined by the 802.3 spec. The 802.3 spec uses the xmit variable to indicate CONFIGURATION (/C/) IDLE (/I/) or Data condition for transmit ...
Description: You can obtain the SGMII IP reference design by downloading the latest version of the SGMII/GbE PCS IP reference design through IPexpress, and by generating the IP core in IPexpress. This will generate a reference design for you. The IP ...
Description: No. The current Lattice CPRI IP core demo has the C&M channels connection ports which can be connected to an HDLC framer and Ethernet MAC core. The demo has its own test pattern generator and checker, but it does not include the HDLC ...
Description: The XAUI PCS communicates the local/remote link fault to the MAC via the XGMII RX data/control bus during the IDLE period, as defined by the IEEE specification. No other signals are used to communicate fault signaling. When the RX MAC ...
Description:The Inter Packet Gap (IPG) shrink (deleting of /I2/ ordered set) will always happens as long as there is a PPM (Part per Million) difference between the local reference clock and the remote reference clock, and the remote reference clock ...
Lattice has a reference design, that can be used as reference for the RGMII in LatticeECP3 device. Refer to FPGA-RD-02136, RGMII to GMII Bridge Design. ...