3819 - LatticeECP3: Does Lattice have a reference design to support Reduced Gigabit Media Independent Interface (RGMII)in LatticeECP3 device?

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  Yes, the SGMII IP (Serial Gigabit Media Independent Interface) of Lattice matches the SGMII 802.3 protocol. According to the description of the Start_of_Packet delimiter (SPD), the PCS (Physical Coding Sublayer) will replace the first octet of the ...

• 7763 - I3C Controller IP - Where can I download the Out of the Box Design Example

  Please refer to below information: I3C IP User Guide : https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/ipcore/ipcores04/i3c-controller Navigate to the IPUG from the link: Documentation > Quick Reference > User Manual > ...

• 1699 - CPRI:  Does the LatticeECP3 CPRI demo reference design work in the Lattice Diamond software?

  Yes. Currently we have the LatticeECP3 CPRI IP demo reference design (version2.0) that is available for download on our website: http://www.latticesemi.com/FileExplorer.aspx?media={A3EB1AA0-3EA0-40D2-8860-ABB289B9E731}&document_id=35086 Note: This ...

• 7743 - How to implement Gigabit Ethernet in Certus-NX, CertusPro-NX, MachXO5-NX and CrossLink-NX FPGAs?

  Lattice currently recommends the following for implementing Gigabit Ethernet interfaces: CertusPro-NX FPGAs: Use SERDES-based SGMII or RGMII Certus-NX, MachXO5-NX, and CrossLink-NX: Use RGMII These recommendations are based on updated LVDS-based ...

• 1296 - Do the Lattice PCIe DevKit endpoint reference designs support Write-Combining transactions?

  Write-Combining allows the CPU to burst 64 byte MWr TLPs to a PCIe endpoint, but there are implications. PC CPUs have a memory caching mode known as Write-Combining (WC). Write Combining allows the memory manager of the CPU to buffer up writes ...