1514 - LatticeSC/M: What effect does a PCS local/remote fault signal to the 10Gb+ Ethernet MAC have on the MAC TX and RX logic?

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• 967 - LatticeECP2/M/LatticeECP3: Does the LatticeECP2M and LatticeECP3 SGMII and Gb Ethernet PCS IP "xmit_autoneg" port indicate autonegotiation [xmit] status as defined by IEEE 802.3 ?

  The SGMII and Gb Ethernet PCS IP "xmit_autoneg" signal does not have the same definition as the xmit variable defined by the 802.3 spec. The 802.3 spec uses the xmit variable to indicate CONFIGURATION (/C/) IDLE (/I/) or Data condition for transmit ...

• 2695 - LatticeECP3:  Can LatticeECP3's 2.5Gbps Ethernet PCS IP and 2.5Gbps Ethernet MAC IP run together at 1 GbE rates?

  The LatticeECP3 2.5 GBE MAC and PCS IPs described in IPUG98 and IPUG99, will run at 1.25 Gbps by changing the ref_clk clock source to 125 Mhz as shown in the "PHY with Host Bus Control Interface" figure of IPUG99. The byte_clk and word_clk will be ...

• 1991 - SGMII and Gb Ethernet PCS IP Core: How many idle ordered sets will the IP's Clock Tolerance Compensation logic insert or delete during an inter-packet gap period?

  The Clock Tolerance Compensation (CTC) logic in the SGMII and Gb Ethernet PCS IP Core performs both idle ordered set insertion when the CTC FIFO low watemark is reached and idle ordered set deletion when the CTC FIFO high watemark is reached. CTC ...

• 6968 - Tri-speed Ethernet MAC: How to resolve Tri-speed Ethernet MAC version 1.4.0 synthesis error?

  Description: Following error is encountered when compiling Radiant project with Tri-speed Ethernet MAC IP version 1.4.0, which is due to invalid .ldc file constraint: Error 1026000 Synthesis ERROR - ...

• 697 - Why do I occasionally see invalid 8b10b characters at the PCS/SERDES QUAD RX FPGA FIFO interface even though the PCS link state machine shows correct status?

  When the Lattice SERDES/PCS QUAD is powered up, the PCS recovered clocks are unstable until the RX CDR locks fully to the incoming data. During the time the RX clocks are unstable, the pointers on the PCS RX FPGA interface FIFO (RX FIFO) can reach ...