Interface & Protocol IPs | DDR2

DDR2
4332 - MachXO3: Is DDR2/3 Memory Interface supported?
MachXO3 devices do not support DDR2/3 memory interface. They do not have DQ/DQs pins that are required for DDR memory interface.
1716 - LatticeECP3: Why do I need to have external VTT termination only on the DDR2/3 (Double Data Rate) data signals at the Lattice FPGA side but not for the address, command and control signals?
DDR (Double Data Rate) memory interfaces use SSTL signaling which requires parallel termination to VTT at the receiver side. The external VTT termination on data is for the memory controller side during the read operations. Since the address, command ...
1710 - LatticeECP3: How do I implement multiple DDR2/3 memory interfaces in one side of LatticeECP3 when there is only one DQSDLL available per side?
LatticeECP3 devices have one DQSDLL per side. DQSDLL has an input port called UDDCNTLN that allows its DLL code value (DQSDEL output) to be updated while it is asserted Low. The updated code value is used to generate precise PVT (Process Voltage ...
304 - DDR2:  What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP core?
There are several possible reasons when the read data valid signal is not asserted at all during the read operation: The read data valid signal is generated from the incoming DQS signal that is driven by a DDR2 memory device or memory module (except ...

Interface & Protocol IPs | DDR2 | Knowledge Base