1710 - LatticeECP3: How do I implement multiple DDR2/3 memory interfaces in one side of LatticeECP3 when there is only one DQSDLL available per side?
LatticeECP3 devices have one DQSDLL per side. DQSDLL has an input port called UDDCNTLN that allows its DLL code value (DQSDEL output) to be updated while it is asserted Low. The updated code value is used to generate precise PVT (Process Voltage Temperature) compensated delays for DDR write and read operations while UDDCNTLN is deasserted High. The memory controller must properly control UDDCNTLN to take advantage of PVT compensated DDR write and read operations. UDDCNTLN must go active only while the memory controller is not performing any DDR read or write operations in order to avoid data corruption that may be caused by dynamic changes of DLL code.
When multiple DDR3 memory interfaces are implemented in either the left or the right side, the DQSDLL in the same side must be shared so that all controllers can utilize the PVT compensation.
If your DDR2/3 memory controller has an active-Low DLL update control output signal and you want to implement N number of memory controller in the same side, each memory controller output can be connected to a N-input OR gate input and the OR gate output is connected to the UDDCNTLN input of the DQSDLL.
If your DDR2/3 memory controller has an active-High DLL update control output signal and you want to implement N number of memory controller in the same side, each memory controller output can be connected to a N-input NAND gate input and the NAND gate output is connected to the UDDCNTLN input of the DQSDLL.