Description: This table is to provide guidelines to help customers select the appropriate Memory Controller IP for Avant devices in accordance to the supported Memory Controller IP version in Radiant Software Tools. User may choose to continue to use ...
Description: The driver API for DDR Memory Controller v2.6.0, DDR_MC_DONE_BITS in ddr_mc_avant.h is incorrect and causing invalid training status. Wrong value: #define DDR_MC_DONE_BITS 0x0000007D Correct value: #define DDR_MC_DONE_BITS 0x0000007F ...
Differential SSTL (Stub Series Terminated Logic) I/O type is specified using a Place and Route (PAR) preference called "IOBUF". You only need to specify the positive-end of the differential SSTL pair in your RTL design. The differential I/O appears, ...
The ECP2 and XP2 have 2 DQSDLLs one on each side of the device which are used compensate for DQS delays. Hence you can have up to 2 different interfaces running at different speeds on a single device. If you need more than one DDR memory interface in ...
When implementing generic DDR interface, it is required that user generate the interface using IPexpress. If not using IPexpress, the user may not implement the DELAYB element to pass the input data through to the IDDRX module. On the LatticeECP2M ...