Description Lattice XO2 and XO3 devices do not natively support the conventional I²C Soft IP provided in Propel. Customers who require I²C functionality must use the reference designs provided by Lattice Semiconductor. To implement I²C communication, ...
Pins A9 & C9 are dual purpose pins that are SCL & SDA for the I2C primary port on the LCMXO2-2000HC-4BG256C and have an absolute maximum rating of -0.25V and -0.3V. Please refer to note 5 of the 'Absolute Maximum Ratings' under the 'DC and Switching ...
As long as the clock speed for the wishbone bus is at least 7.5x higher than the I2C (SCL) bus speed, there shouldn't be any issue. To further check this, it is recommend to perform Gate-Level Timing Simulation.
Description: The Lattice I2C Master IP core is limited only for 8-bits at maximum of 255 bytes. If you want to have an I2C transactions using >/= 256 bytes, you will need to start a new or next transaction using CONTROL_REG.start.
Description: The I2C Master IP from Lattice does not support repeated start to allow a read then write or a write then read command. Solution: A workaround for this is to perform separate start-stop transactions, refer to FPGA-IPUG-02071 section 2.5. ...