6465 - Lattice Nexus FPGA Families: Does I2C Master Core IP allows transaction for more than or equal to 256 bytes?

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• 6458 - CrossLink-NX: Why does I2C Master Core IP does not have documentation about I2C repeated start?

  Description: The I2C Master IP from Lattice does not support repeated start to allow a read then write or a write then read command. Solution: A workaround for this is to perform separate start-stop transactions, refer to FPGA-IPUG-02071 section 2.5. ...

• 1748 - Common Public Radio Interface - IP Core: Do I need to use a clock cleaner when using CPRI IP core (Common Public Radio Interface) with Lattice SERDES based FPGA?

  Lattice CPRI IP core (Common Public Radio Interface) supports LatticeECP2/M, LatticeECP3 and LatticeSC. When using the CPRI IP core in REC(Radio Equipment Control,master) mode, it's not necessary to use a clock cleaner since the system provides the ...

• 2319 - [LatticeECP3]: Should I reset the Lattice DDR3 controller IP core after changing the "read_pulse_tap" signal?

  The "read_pulse_tap" port is an input signal to the DDR3 controller IP core. Each DQS group has its own 3-bit read_pulse_tap port to control the READ signal timing to the DQSBUF hardware module. The DDR3 IP core allows dynamic READ pulse timing ...

• 1061 - Lattice All FPGAs: Which device is the minimal device needed to support PCI Express x1 and x4 core?

  The PCI Express x1 and x4 IP Core is supported by both SC and ECP2 device families. The minimal ECP2M device needed to support the core is LFE2M-20E-6F484C, and the minimal SC device needed is LFSC3GA15E-6F900C. Newer Lattice FPGA families that ...

• 2244 - LatticeECP3: I need to use four chip select signals while the Lattice DDR3 controller IP core supports only up to two. Can I extend the number of chip select from the core?

  Description: No. Lattice DDR3 controller IP core does not support more than 2 chip selects. The IP core was designed and validated to support upto two ranks of DDR3 memory configurations. Since each rank is controlled by a corresponding chip select ...